HYS64T32900 Overview
Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module HYS64T32[0/9]00EU-[25F/2.5/3/3S/3.7]-B2, HYS[64/72]T64[0/9]00EU-[25F/2.5/3/3S/3.7]-B2, HYS[64/72]T128[0/9]20EU[25F/2.5/3/3S/3.7]-B2 Revision History: Added 6LayerWhiteBox Products Block Diagrams: Clock Signal Load Tables and Notes updated ODT table update Added IDD values SPD codes updated Previous Revision:.
HYS64T32900 Key Features
- Auto Refresh (CBR) and Self Refresh Programmable self refresh rate via EMRS2 setting Programmable partial array refresh
- 240-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2 SDRAM memory modules
- Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply
- 256MB, 512MB and 1GB modules built with 512-Mbit DDR2 SDRAMs in P-TFBGA-60 and PG-TFBGA-84 chipsize packages
- All speed grades faster than DDR2-400 ply with DDR400 timing specifications
- Programmable CAS Latencies (3, 4, 5 and 6), Burst Length (8 & 4) and Burst Type
- 333 333 200 12 12 45 57 -3S PC2-530