* Programmable self refresh rate via EMRS2 setting
* Programmable partial array refresh via EMRS2 settings
* Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9µs between 85°C and 95°C.
* DCC enabling via EMRS2 setting
* All inputs and outputs SSTL_1
HYS64T256022EDL-2.5-B Datasheet (2.40 MB)
HYS64T256022EDL-2.5-B
Qimonda AG
2.40 MB
200-pin dual die small-outline-ddr2-sdram modules.
November 2006 www.DataSheet4U.com HYS64T256022EDL [25F/2.5] B HYS64T256022EDL [3/3S] B HYS64T256022EDL 3.7
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