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Ramtron International Corporation

FM21L16 Datasheet Preview

FM21L16 Datasheet

2Mbit FRAM Memory

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Preliminary
FM21L16
2Mbit FRAM Memory
Features
2Mbit Ferroelectric Nonvolatile RAM
Organized as 128Kx16
Configurable as 256Kx8 Using /UB, /LB
1014 Read/Write Cycles
NoDelay™ Writes
Page Mode Operation to 40MHz
Advanced High-Reliability Ferroelectric Process
SRAM Compatible
Industry Std. 128Kx16 SRAM Pinout
60 ns Access Time, 110 ns Cycle Time
Advanced Features
Low VDD Monitor Protects Memory against
Inadvertent Writes
Software Programmable Block Write Protect
Description
The FM21L16 is a 128Kx16 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or FRAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and high write endurance make
FRAM superior to other types of memory.
In-system operation of the FM21L16 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The FRAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM21L16 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in the form of an SRAM.
The FM21L16 includes a low voltage monitor that
blocks access to the memory array when VDD drops
below a critical threshold. The memory is protected
against an inadvertent access and data corruption
under this condition. The device also features
software-controlled write protection. The memory
Superior to Battery-backed SRAM Modules
No Battery Concerns
Monolithic Reliability
True Surface Mount Solution, No Rework Steps
Superior for Moisture, Shock, and Vibration
Low Power Operation
2.7V – 3.6V Power Supply
Low Current Mode (5µA) using ZZ pin
18 mA Active Current
Industry Standard Configuration
Industrial Temperature -40° C to +85° C
44-pin “Green”/RoHS TSOP-II package
array is divided into 8 uniform blocks, each of which
can be individually write protected.
The device is available in a 400 mil 44-pin TSOP-II
surface mount package. Device specifications are
guaranteed over industrial temperature range –40°C
to +85°C.
Pin Configuration
Ordering Information
FM21L16-60-TG 60 ns access, 44-pin
“Green”/RoHS TSOP-II
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.0
Sept. 2007
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 14




Ramtron International Corporation

FM21L16 Datasheet Preview

FM21L16 Datasheet

2Mbit FRAM Memory

No Preview Available !

www.DataSheet4U.com
A(16:0)
A(16:2)
A(1:0)
FM21L16 - 128Kx16 FRAM
16K x 16 block 16K x 16 block
16K x 16 block 16K x 16 block
16K x 16 block 16K x 16 block
16K x 16 block 16K x 16 block
CE
WE
UB, LB 2
OE
ZZ
Control
Logic
Column Decoder
I/O Latch & Bus Driver
DQ(15:0)
Figure 1. Block Diagram
Pin Description
Pin Name Type
A(16:0)
Input
/CE Input
/WE Input
/OE Input
/ZZ Input
DQ(15:0)
/UB
/LB
VDD
VSS
I/O
Input
Input
Supply
Supply
Pin Description
Address inputs: The 17 address lines select one of 131,072 words in the FRAM array.
The lowest two address lines A(1:0) may be used for page mode read and write
operations.
Chip Enable input: The device is selected and a new memory access begins when /CE is
low and /ZZ is high. The entire address is latched internally on the falling edge of /CE.
Subsequent changes to the A(1:0) address inputs allow page mode operation when /CE
is low.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM21L16 to write the data on the DQ bus to the FRAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
Output Enable: When /OE is low, the FM21L16 drives the data bus when valid read
data is available. Deasserting /OE high tri-states the DQ pins.
Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest supply
current condition. Since this input is logically AND’d with /CE, /ZZ must be high for
normal read/write operation. If unused, tie /ZZ to VDD.
Data: 16-bit bi-directional data bus for accessing the FRAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z
if /UB is high.
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z
if /LB is high.
Supply Voltage: 3.3V
Ground
Rev. 1.0
Sept. 2007
Page 2 of 14


Part Number FM21L16
Description 2Mbit FRAM Memory
Maker Ramtron International Corporation
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