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Renesas Electronics Components Datasheet

552-02S Datasheet

Low Skew 2-input MUX and 1 to 8 Clock Buffer

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Low Skew 2-input MUX and 1 to 8 Clock Buffer 552-02S
DATASHEET
Description
The 552-02S is a low skew, single-input to eight- output clock
buffer. The device offers a dual input with pin select for
switching between two clock sources. It has best in class
Additive Phase Jitter of sub 50fsec
IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize clocks.
Contact us for all of your clocking needs.
Features
Low RMS Additive Phase Jitter: 50fs
Low output skew: 50ps
Operating Voltages of 1.8V to 3.3V
Packaged in 16-pin TSSOP and 16-pin VFQFN, Pb-free
Input clock multiplexer simplifies clock selection
Output Enable pin tri-states outputs
Input/Output clock frequency up to 200 MHz
Low power CMOS technology
3.3V tolerant inputs
Extended temperature (-40°C to +105°C)
Block Diagram
Q0
Q1
Q2
INA
1
Q3
INB
0
Q4
Q5
Q6
Q7
SELA
OE
552-02S APRIL 18, 2017
1
©2017 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

552-02S Datasheet

Low Skew 2-input MUX and 1 to 8 Clock Buffer

No Preview Available !

552-02S DATASHEET
Pin Assignments
OE 1
VDD 2
Q0 3
Q1 4
Q2 5
Q3 6
GND 7
INB 8
16 SELA
15 VDD
14 Q7
13 Q6
12 Q5
11 Q4
10 GND
9 INA
OE
VDD
Q0
Q1
16 15 14 13
1
12
2
11
3
10
4
9
56 78
Q5
Q4
GND
INA
16 Pin TSSOP
Input Source Select
16-pin VFQFN
SELA
0
1
Input
INB
INA
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
OE
VDD
Q0
Q1
Q2
Q3
GND
INB
INA
GND
Q4
Q5
Q6
Q7
VDD
SELA
Pin
Type
Input
Power
Output
Output
Output
Output
Power
Input
Input
Power
Output
Output
Output
Output
Power
Input
Pin Description
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
Connect to +1.8V, +2.5V or +3.3V. Must be the same as pin 15.
Clock Output 0.
Clock Output 1.
Clock Output 2.
Clock Output 3.
Connect to ground.
Clock Input B. 3.3V tolerant.
Clock Input A. 3.3V tolerant.
Connect to ground.
Clock Output 4.
Clock Output 5.
Clock Output 6.
Clock Output 7.
Connect to +1.8V, +2.5V or +3.3V. Must be the same as pin 2.
Selects either INA or INB. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01F should be
connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and GND on pin 10, as close to the device
as possible. A 33 series terminating resistor should be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the 552-02S is capable of, careful attention must be paid to board layout. Essentially, all 8
outputs must have identical terminations, identical loads, and identical trace geometries. If they do not, the output skew will be
degraded. For example, using a 30series termination on one output (with 33on the others) will cause at least 15ps of skew.
LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER
2
APRIL 18, 2017



Part Number 552-02S
Description Low Skew 2-input MUX and 1 to 8 Clock Buffer
Maker Renesas
Total Page 3 Pages
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552-02S Datasheet PDF





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