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5P1105 Datasheet

Programmable Fanout Buffer

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Programmable Fanout Buffer
5P1105
DATASHEET
Description
The 5P1105 is a programmable fanout buffer intended for
high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface.
The outputs are generated from a single reference clock. The
reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2
17
3
16
EPAD
4
15
5
14
6
13
7 8 9 10 11 12
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
Features
Up to four high performance universal differential output
pairs
– Low RMS additive phase jitter: 0.2ps
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
One additional LVCMOS output clock
Four universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
24-pin VFQFPN
5P1105 FEBRUARY 21, 2019
1
©2019 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

5P1105 Datasheet

Programmable Fanout Buffer

No Preview Available !

5P1105 DATASHEET
Functional Block Diagram
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
VDDD
Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1 GbE and 10 GbE
OTP
and
Control Logic
VDDO0
OUT0_SEL_I2CB
VDDO1
OUT1
OUT1B
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
VDDO4
OUT4
OUT4B
PROGRAMMABLE FANOUT BUFFER
2
FEBRUARY 21, 2019


Part Number 5P1105
Description Programmable Fanout Buffer
Maker Renesas
Total Page 3 Pages
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