low skew 1 to 4 clock buffer.
* Low additive phase jitter RMS: 50fs
* Extremely low skew outputs (50ps)
* Low cost clock buffer
* Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
* In.
The 621S is a low cost, high-speed single input to four output clock buffer. The 621S has best in class Additive Phase Jitter of sub 50fsec.
IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clo.
Image gallery
TAGS
Download (Size : 377.33KB)