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Renesas Electronics Components Datasheet

650R-07ILF Datasheet

NETWORKING CLOCK SOURCE

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NETWORKING CLOCK SOURCE
DATASHEET
ICS650-07C
Description
The ICS650-07C is a low cost, low jitter, high performance
clock synthesizer for networking applications. Using analog
Phase-Locked Loop (PLL) techniques, the device accepts a
12.5 MHz or 25.00 MHz clock or fundamental mode crystal
input to produce multiple output clocks for networking chips,
PCI devices, SDRAM, and ASICs. The ICS650-07C outputs
all have 0 ppm synthesis error.
See the MK74CB214, ICS551, and ICS552-01 for non-PLL
buffer devices which produce multiple low-skew copies of
these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay buffers
that can synchronize outputs and other needed clocks.
Block Diagram
Features
Packaged in 20-pin tiny SSOP (QSOP)
Pb (lead) free package
12.5 MHz or 25.00 MHz fundamental crystal or clock
input
Six output clocks with selectable frequencies
SDRAM frequencies of 67, 83, 100, and 133 MHz
Buffered crystal reference output
Zero ppm synthesis error in all clocks
Ideal for PMC-Sierra’s ATM switch chips
Full CMOS output swing with 25 mA output drive
capability at TTL levels
Advanced, low power, sub-micron CMOS process
3.0 V to 5.5 V operating voltage
VDD
2
CLKA1
2
ACS1, 0
2
BCS1, 0
CCS
Clock
Synthesis
and Control
Circuitry
12.5 MHz or 25.00 MHz
Crystal or Clock
X1/ICLK
X2
Clock
Buffer/
Crystal
Oscillator
Optional crystal capacitors are shown and
may be required for tuning of initial accuracy
2
GND
/2
CLKA2
CLKB1
/2
CLKB2
CLKC1
CLKC2
REFOUT
OE (all outputs)
IDT™ / ICS™ NETWORKING CLOCK SOURCE
1
ICS650-07C REV D 102709


Renesas Electronics Components Datasheet

650R-07ILF Datasheet

NETWORKING CLOCK SOURCE

No Preview Available !

ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Pin Assignment
ACS0
1
X2
2
X1/ICLK
3
VDD
4
ACS1
5
GND
6
CLKC1
7
CLKC2
8
CLKB2
9
CLKB1
10
20
BCS1
19
BCS0
18
REFOUT
17
CLKA1
16
VDD
15
OE
14
GND
13
CLKA2
12
DC
11
CCS
20 pin (150 mil) SSOP
Pin Descriptions
Pin Name Pin Type
Description
1
ACS0 Tri-level Input A clock select 0. Selects outputs on CLKA1 and CLKA2. See table below.
2
X2
XO
Crystal connection. Connect to a crystal or leave unconnected for clock input.
3 X1/ICLK
XI
Crystal connection. Connect to fundamental crystal or clock input.
4
VDD
Power Connect to 3.3 V or 5 V. Must be same value as other VDD.
5
ACS1
Input
A clock select 1. Selects outputs on CLKA1 and CLKA2. Internal pull-up
resistor. See table below.
6
GND
Power Connect to ground.
7
CLKC1
Output Clock C output 1. Depends on setting of CCS per table below.
8
CLKC2
Output Clock C output 2. Depends on setting of CCS per table below. Same as CLKC1.
9
CLKB2
Output Clock B output 2. Depends on setting of BCS1, 0 per table below.
10 CLKB1
Output Clock B output 1. Depends on setting of BCS1, 0 per table below.
11
CCS Tri-level Input Clock C Select pin. Selects outputs on CLKC1 and CLKC2 per table below.
12
DC
Don’t Connect. Do not connect anything to this pin.
13 CLKA2
Output Clock A output 2. Depends on setting of ACS1, 0 per table below.
14
GND
Power Connect to ground.
15
OE
Input
Output enable. Tri-states all outputs when low. Internal pull-up resistor.
16
VDD
Power Connect to VDD. Must be same value as other VDD.
17 CLKA1
Output Clock A output 1. Depends on setting of ACS1, 0 per table below.
18 REFOUT
Output Buffered reference clock output. Same frequency as crystal or clock input.
19
BCS0 Tri-level Input B clock select 0. Selects outputs on CLKB1 and CLKB2. See table below.
20
BCS1
Input
B clock select 1. Selects outputs on CLKB1 and CLKB2. See table below.
IDT™ / ICS™ NETWORKING CLOCK SOURCE
2
ICS650-07C REV D 102709


Part Number 650R-07ILF
Description NETWORKING CLOCK SOURCE
Maker Renesas
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