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NETWORKING CLOCK SOURCE
DATASHEET
ICS650-07C
Description
The ICS650-07C is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25.00 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-07C outputs all have 0 ppm synthesis error. See the MK74CB214, ICS551, and ICS552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the ICS570, ICS9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.
Block Diagram
Features
• Packaged in 20-pin tiny SSOP (QSOP) • Pb (lead) free package • 12.5 MHz or 25.
650R-07LF Datasheet
