7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Description
The IDT7006 is a high-speed 16K x 8 Dual-Port Static RAM. The
IDT7006 is designed to be used as a stand-alone 128K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
Military, Industrial and Commercial Temperature Ranges
a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 750mW of power. Low-power (L) versions
offer battery backup data retention capability with typical power consump-
tion of 500µW from a 2V battery.
The IDT7006 is packaged in a ceramic 68-pin PGA, an 68-pin quad
flatpack, a PLCC, and a 64-pin thin quad flatpack, TQFP. Military grade
product is manufactured in compliance with the latest revision of MIL-PRF-
38535 QML, Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
I/O7R
N/C
OER
R/WR
SEMR
CER
N/C
A13R
GND
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
27
9
28
8
29
7
30
6
31
5
32
4
33
3
34
35
7006
PLG68(4)
2
1
36
68
68-Pin PLCC
37
Top View
67
38
66
39
65
40
64
41
63
42
62
43
44 45
46 47
48
49
50 51
52
53
54
55
56 57
58
59
6061
I/O1L
I/O0L
N/C
OEL
R/WL
SEML
CEL
N/C
A13L
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
2739 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PLG68 package body is approximately .95 in x .95 in. x .17 in.
FP68 package body is approximately .97 in x .97 in x .08 in.
4. This package code is used to reference the package diagram.
A6L
A7L
A8L
A9L
A10L
A11L
A12L
VCC
A13L
N/C
CEL
SEML
R/WL
OEL
N/C
I/O0L
I/O1L
61 60
59
58
57
56
55
54 53
52
51 50
49
48
47
46
45
44
43
62
42
63
41
64
40
65
39
66
38
67
37
68
1
7006
36
FP68(4)
35
2
34
3
68 Pin Flatpack
33
4
Top View
32
5
31
6
30
7
29
8
28
9
27
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A5R
A6R
A7R
A8R
A9R
A10R
A11R
A12R
GND
A13R
N/C
CER
SEMR
R/WR
OER
N/C
I/O7R
2739 drw 02a
2
Jan.30.20
