7026L Datasheet | Renesas

Features - True Dual-Ported memory cells which allow simultaneous access of the same memory location - High-speed access - mercial: 15/20/25/35ns (max.) - Industrial: 20ns (max.) - Military: 25/35ns (max.) - Low-power operation - IDT7026S Active: 750m W (typ.) Standby: 5m W (typ.) - IDT7026L Active: 750m W (typ.) Standby: 1m W (typ.) - Separate upper-byte and lower-byte control for multiplexed bus patibility Functional Block Diagram R/WL UBL - IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device - M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave - On-chip port arbitration logic - Full on-chip hardware support of semaphore signaling between ports - Fully asynchronous operation from either port - TTL-patible, single 5V (±10%) power supply - Available in 84-pin PGA and 84-pin PLCC - Industrial temperature range (-40°C to +85°C) is available for selected speeds - Green parts available, see ordering information R/WR UBR I/O8L-I/O15L I/O0L-I/O7L BUSYL(1,2) A13L A0L I/O Control I/O Control Address Decoder MEMORY ARRAY ARBITRATION SEMAPHORE LOGIC Address...