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Renesas Electronics Components Datasheet

70T3719M Datasheet

DUAL-PORT STATIC RAM

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HIGH-SPEED 2.5V
70T3719/99M
256/128K x 72
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)
4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timed write allows fast cycle time
Functional Block Diagram
BE7L
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz
Available in a 324-pin Green Ball Grid Array (BGA)
Includes JTAG Functionality
Green parts available, see ordering information
BE7R
BE0L
BE0R
FT/PIPEL
0a 1a
1/0
a
0h 1h
h
1h 0h
h
1a 0a
1/0
a
FT/PIPER
R/WL
R/WR
CE0L
CE1L
OEL
FT/PIPEL
1
0
1/0
1h 0h
0/1
a
1a 0a
h
Byte 0
I/O0L - I/O71L
CLKL
A17L(1)
A0L
REPEATL
ADSL
CNTENL
Byte 7
Counter/
Address
Reg.
B
B
B
B
W
WW
W
0
7
7
0
L
L
R
R
DOUT0-8_L
DOUT9-17_L
DOUT18-26_L
DOUT27-35_L
DOUT36-44_L
DOUT45-53_L
DOUT54-62_L
DOUT63-72_L
DOUT0-8_R
DOUT9-17_R
DOUT18-26_R
DOUT27-35_R
DOUT36-44_R
DOUT45-53_R
DOUT54-62_R
DOUT63-72_R
256/128K x 72
MEMORY
ARRAY
DIN_L
DIN _R
ADDR_L
ADDR_R
1
0
1/0
0a 1a
h
0h 1h
0/1
a
Byte 7
Counter/
Address
Reg.
Byte 0
I/O0R - I/O71R
,
CLKR
A17R(1)
A 0R
REPEATR
ADSR
CNTENR
CE0R
CE1R
OER
,
FT/PIPER
COL L
INTL
CE0L
CE1L
R/WL
INTERRUPT
COLLISION
DETECTION
LOGIC
CE0R
CE1R
R/WR
COL R
INTR
NOTES:
ZZL(2)
ZZ
CONTROL
LOGIC
ZZR(2)
1. Address A17 is a NC for the IDT70T3799.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
©2019 Integrated Device Technology, Inc.
TDI
TCK
JTAG
T MS
TDO
T RST
5687 drw 01
NOVEMBER 2019
DSC 5687/6


Renesas Electronics Components Datasheet

70T3719M Datasheet

DUAL-PORT STATIC RAM

No Preview Available !

70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70T3719/99M is a high-speed 256K/128K x 72 bit synchro-
nous Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times. With an input data register, the
IDT70T3719/99M has been optimized for applications having unidirec-
tional or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70T3719/99M can support an operating voltage of either 3.3V
or 2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (VDD) is at 2.5V.
6.422



Part Number 70T3719M
Description DUAL-PORT STATIC RAM
Maker Renesas
Total Page 3 Pages
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