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71V424S Datasheet

3.3V CMOS Static RAM

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3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
71V424S
71V424L
Features
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
Description
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
as 512K x 8. It is fabricated using high-performance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71V424 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
pin, 400 mil TSOP.
A0
ADDRESS
DECODER
A18
4,194,304-BIT
MEMORY ARRAY
I/O0 - I/O7
WE
OE
CS
8
8
CONTROL
LOGIC
8
I/O CONTROL
3622 drw 01
1
May.04.21


Renesas Electronics Components Datasheet

71V424S Datasheet

3.3V CMOS Static RAM

No Preview Available !

71V424S, 71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Pin Configurations(1)
A0
1
36
NC
A1
2
35
A18
A2
3
34
A17
A3
4
33
A16
A4
5
CS
6
32
A15
31
OE
I/O0
7
71V424
30
I/O7
I/O1
8
PBG36
29
I/O6
VDD
9
28
VSS
VSS
10
27
VDD
I/O2
11
26
I/O5
I/O3
12
WE
13
25
I/O4
24
A14
A5
14
23
A13
A6
15
22
A12
A7
16
21
A11
A8
17
20
A10
A9
18
19
NC
SOJ
3622 drw 02
Top View
NOTE:
1. This text does not indicate orientation of actual part-marking.
Commercial and Industrial Temperature Ranges
NC
1
NC
2
A0
3
A1
4
A2
5
A3
6
A4
7
CS
8
I/00
9
I/01
10
VDD
11
VSS
12
I/02
13
I/03
14
WE
15
A5
16
A6
17
A7
18
A8
19
A9
20
NC
21
NC
22
44
NC
43
NC
42
NC
41
A18
40
A17
39
A16
38
A15
37
OE
36
I/07
71V424
35
I/06
PHG44
34
VSS
33
VDD
32
I/05
31
I/04
30
A14
29
A13
28
A12
27
A11
26
A10
25
NC
24
NC
23
NC
TSOP
3622 drw 11
Top View
Pin Description
A0 – A18
Address Inputs
CS
Chip Select
WE
Write Enable
OE
Output Enable
I/O0 - I/O7
Data Input/Output
VDD
3.3V Power
VSS
Ground
May.04.21
Input
Input
Input
Input
I/O
Power
Gnd
3622 tbl 02
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol
Parameter(1)
Conditions
Max. Unit
CIN Input Capacitance
VIN = 3dV
7 pF
CI/O I/O Capacitance
VOUT = 3dV
8 pF
NOTE:
3622 tbl 03
1. This parameter is guaranteed by device characterization, but not production
tested.
Truth Table(1,2)
CS
OE
WE
I/O
Function
L
L
H
DATAOUT Read Data
L
X
L
DATAIN Write Data
L
H
H
High-Z Output Disabled
H
X
X
High-Z Deselected - Standby (ISB)
VHC(3 )
X
X
High-Z Deselected - Standby (ISB1)
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VDD -0.2V.
3. Other inputs VHC or VLC.
3622 tbl 01
6.242


Part Number 71V424S
Description 3.3V CMOS Static RAM
Maker Renesas
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71V424S Datasheet PDF






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