72V221 Datasheet | Renesas

3.3 VOLT CMOS Sync FIFO™ 256 x 9, 512 x 9, IDT72V201, IDT72V211 1,024 x 9, 2,048 x 9, IDT72V221, IDT72V231 4,096 x 9 and 8,192 x 9 IDT72V241, IDT72V251 LEAD FINISH (Sn Pb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Features : - 256 x 9-bit organization IDT72V201 - 512 x 9-bit organization IDT72V211 - 1,024 x 9-bit organization IDT72V221 - 2,048 x 9-bit organization IDT72V231 - 4,096 x 9-bit organization IDT72V241 - 8,192 x 9-bit organization IDT72V251 - 10 ns read/write cycle time - 5V input tolerant - Read and Write clocks can be independent - Dual-Ported zero fall-through time architecture - Empty and Full Flags signal FIFO status - Programmable Almost-Empty and Almost-Full flags can be set to any depth - Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively - Output Enable puts output data bus in high-impedance state - Advanced submicron CMOS technology - Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin plastic Thin Quad Flat Pack (TQFP) - Industrial temperature range (- 40°C to +85°C) is available - Green parts available, see ordering...