74FCT38072S Datasheet - Renesas

Low Skew 1 to 2 Clock Buffer

74FCT38072S Features

* Low additive phase jitter RMS: 50fs

* Extremely low skew outputs (50ps)

* Low cost clock buffer

* Packaged in 8-pin SOIC and 8-pin DFN, Pb-free

* Input/Output clock frequency up to 200 MHz

* Low power CMOS technology

* Operating voltages of 1

74FCT38072S General Description

The 74FCT38072S is a low skew, single input to two output, clock buffer. The 74FCT38072S has best in class additive phase Jitter of sub 50 fsec. Renesas makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking n.

74FCT38072S Datasheet (529.58 KB)