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Renesas Electronics Components Datasheet

79RC32355 Datasheet

Communications Processor

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IDTTM InterpriseTM Integrated
Communications Processor
79RC32355
Features List
RC32300 32-bit Microprocessor
– Enhanced MIPS-II ISA
– Enhanced MIPS-IV cache prefetch instruction
– DSP Instructions
– MMU with 16-entry TLB
– 8KB Instruction Cache, 2-way set associative
– 2KB Data Cache, 2-way set associative
– Per line cache locking
– Write-through and write-back cache management
– Debug interface through the EJTAG port
– Big or Little endian support
Interrupt Controller
– Allows status of each interrupt to be read and masked
I2C
– Flexible I2C standard serial interface to connect to a variety of
peripherals
– Standard and fast mode timing support
– Configurable 7 or 10-bit addressable slave
UARTs
– Two 16550 Compatible UARTs
– Baud rate support up to 1.5 Mb/s
Counter/Timers
– Three general purpose 32-bit counter/timers
General Purpose I/O Pins (GPIOP)
– 36 individually programmable pins
– Each pin programmable as input, output, or alternate function
– Input can be an interrupt or NMI source
– Input can also be active high or active low
Block Diagram
SDRAM Controller
– 2 memory banks, non-interleaved, 512 MB total
– 32-bit wide data path
– Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
– SODIMM support
– Stays on page between transfers
– Automatic refresh generation
Peripheral Device Controller
– 26-bit address bus
– 32-bit data bus with variable width support of 8-,16-, or 32-bits
– 8-bit boot ROM support
– 6 banks available, up to 64MB per bank
– Supports Flash ROM, PROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation, Intel or Motorola style
– Write protect capability
– Direct control of optional external data transceivers
System Integrity
– Programmable system watchdog timer resets system on time-
out
– Programmable bus transaction times memory and peripheral
transactions and generates a warm reset on time-out
DMA
– 16 DMA channels
– Services on-chip and external peripherals
– Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O
transfers
– Supports flexible descriptor based operation and chaining via
linked lists of records (scatter / gather capability)
– Supports unaligned transfers
– Supports burst transfers
RC32300
CPU Core
ICE
EJTAG MMU
D. Cache I. Cache
Interrupt
:
Controller :
3 Counter
Timers
Watchdog
Timer
10/100
Ethernet
Interface
USB
Interface
16 Channel
DMA
Controller
Arbiter
Ext. Bus
Master
SDRAM &
Device
Controller
I2C
Controller
2 UARTS
(16550)
GPIO
Interface
TDM
Interface
ATM
Interface
Memory & I2C Bus
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins TDM Bus
Figure 1 RC32355 Internal Block Diagram
Utopia 1 / 2
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 47
May 25, 2004
DSC 5900


Renesas Electronics Components Datasheet

79RC32355 Datasheet

Communications Processor

No Preview Available !

IDT 79RC32355
USB
– Revision 1.1 compliant
– USB slave device controller
– Supports a 6th USB endpoint
– Full speed operation at 12 Mb/s
– Supports control, interrupt, bulk and isochronous endpoints
– Supports USB remote wakeup
– Integrated USB transceiver
TDM
– Serial Time Division Multiplexed (TDM) voice and data inter-
face
– Provides interface to telephone CODECs and DSPs
– Interface to high quality audio A/Ds and D/As with external
glue logic
– Support 1 to 128 8-bit time slots
– Compatible with Lucent CHI, GCI, Mitel ST-bus, K2 and SLD
busses
– Supports data rates of up to 8.192 Mb/s
– Supports internal or external frame generation
– Supports multiple non-contiguous active input and output time
slots
EJTAG
– Run-time Mode provides a standard JTAG interface
– Real-Time Mode provides additional pins for real-time trace
information
Ethernet
– Full duplex support for 10 and 100 Mb/s Ethernet
– IEEE 802.3u compatible Media Independent Interface (MII)
with serial management interface
– IEEE 802.3u auto-negotiation for automatic speed selection
– Flexible address filtering modes
– 64-entry hash table based multicast address filtering
ATM SAR
– Can be configured as one UTOPIA level 1 interface or 1
UTOPIA level 2 interface with 2 address lines (3 PHYs max)
– Supports 25Mb/s and faster ATM
– Supports UTOPIA data path interface operation at speeds up
to 33 MHz
– Supports standard 53-byte ATM cells
– Performs HEC generation and checking
– Cell processing discards short cells and clips long cells
– 16 cells worth of buffering
– UTOPIA modes: 8 cell input buffer and 8 cell output buffer
– Hardware support for CRC-32 generation and checking for
AAL5
– Hardware support for CRC-10 generation and checking
– Virtual caching receive mechanism supports reception of any
length packet without CPU intervention on up to eight simulta-
neously active receive channels
– Frame Mode transmit mechanism supports transmission of
any length packet without CPU intervention
System Features
– JTAG Interface (IEEE Std. 1149.1 compatible)
– 208 pin PQFP package
– 2.5V core supply and 3.3V I/O supply
– Up to 180 MHz pipeline frequency and up to 75 MHz bus
frequency
Debug port
USB to PC
Echo
RC32300 CPU Core
Timers
UART
Interrupt Ctl
DMA
Channels
USB
Data Buffers
SDRAM Ctl
Memory &
I/O Controller
TDM
ATM I/F
Clock
32-bit Data Bus
SDRAM
Memory & I/O
Transmission
Convergence
Codec
SLIC
Ethernet MAC
MII I/F
Ethernet Transceiver
Data Pump
AFE
POTS telephone
RJ11
Ethernet to PC
Figure 2 Example of xDSL Residential Gateway Using RC32355
2 of 47
May 25, 2004


Part Number 79RC32355
Description Communications Processor
Maker Renesas
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79RC32355 Datasheet PDF






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