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IDTTM InterpriseTM Integrated Communications Processor
79RC32355
Features List
◆ RC32300 32-bit Microprocessor – Enhanced MIPS-II ISA – Enhanced MIPS-IV cache prefetch instruction – DSP Instructions – MMU with 16-entry TLB – 8KB Instruction Cache, 2-way set associative – 2KB Data Cache, 2-way set associative – Per line cache locking – Write-through and write-back cache management – Debug interface through the EJTAG port – Big or Little endian support
◆ Interrupt Controller – Allows status of each interrupt to be read and masked
◆ I2C – Flexible I2C standard serial interface to connect to a variety of peripherals – Standard and fast mode timing support – Configurable 7 or 10-bit addressable slave
◆ UARTs – Two 16550 Compatible UARTs – Baud rate support up to 1.