82P33741 Datasheet | Renesas

FEATURES - Differential reference inputs (IN1 to IN6) accept clock frequencies between 2 k Hz and 650 MHz - Single ended inputs (IN7 to IN12) accept reference clock frequencies between 2 k Hz and 162.5 MHz - Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input - Reference monitors qualify/disqualify references depending on activity, frequency and LOS pins - Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings - Fractional-N input dividers enable the DPLLs to lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G/ 40G/100G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM and GNSS frequencies - Any reference inputs (IN1 to IN12) can be designated as external sync pulse inputs (1 PPS, 2 k Hz, 4 k Hz or 8 k Hz) associated with a selectable reference clock input - FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses that are aligned with the selected external input sync pulse input and frequency locked to the associated reference clock input - DPLL1 and DPLL2 can be configured with bandwidths between 18 Hz and 567 Hz - DPLL1 and DPLL2 lock to input references with frequencies between 2 k Hz and 650 MHz - DPLL3 locks to input references with frequencies between 8 k Hz and 650 MHz - DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/ OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks are directly available on OUT1 - DPLL3 generates N x 8 k Hz clocks up to 100 MHz that are output on OUT8 and OUT9 - APLL1, APLL2 and APLL3 can be connected to DPLL1 and DPLL2 - APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or SONET/SDH frequencies - APLL3 generates 10G/40G/100G Ethernet, WAN-PHY and LAN-PHY frequencies - Any of eight mon TCXO/OCXO frequencies can be used for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or...