82P33741 Description
Port Synchronizer for IEEE 1588 and 10G/ 40G/ 100G Synchronous Ethernet 82P33741 Datasheet HIGHLIGHTS DPLL1 and DPLL2 can be used on line cards to manage the generation of synchronous port clocks and IEEE 1588 synchronization signals based on multiple system backplane references DPLL3 can be used on line cards to select ining line clocks for use on system backplanes; it can also be used for general purpose timing...
82P33741 Key Features
- Differential reference inputs (IN1 to IN6) accept clock frequencies between 2 kHz and 650 MHz
- Single ended inputs (IN7 to IN12) accept reference clock frequencies between 2 kHz and 162.5 MHz
- Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any clock reference input
- Reference monitors qualify/disqualify references depending on activity, frequency and LOS pins
- Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors,
- Fractional-N input dividers enable the DPLLs to lock to a wide range of reference clock frequencies including: 10/100/10
- Any reference inputs (IN1 to IN12) can be designated as external sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associ
- FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses that are aligned with the selected external input sync pulse input
- DPLL1 and DPLL2 can be configured with bandwidths between 18 Hz and 567 Hz
- DPLL1 and DPLL2 lock to input references with frequencies between 2 kHz and 650 MHz