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82V3001A - WAN PLL

Datasheet Summary

Description

The IDT82V3001A is a WAN PLL with single reference input.

It contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference.

Features

  • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces.
  • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timingfor E1 interface.
  • Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048 MHz.
  • Provides eight types of clock signals: C1.5o, C3o, C2o, C4o, C6o, C8o, C16o and C32o.
  • Provides six types of 8 kHz framing pulses: F0o, F8o, F16o, F32o, RSP and TSP.
  • Holdover frequency accuracy.

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Datasheet Details

Part number 82V3001A
Manufacturer Renesas
File Size 284.89 KB
Description WAN PLL
Datasheet download datasheet 82V3001A Datasheet
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WAN PLL WITH SINGLE REFERENCE INPUT IDT82V3001A FEATURES • Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timingfor E1 interface • Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048 MHz • Provides eight types of clock signals: C1.5o, C3o, C2o, C4o, C6o, C8o, C16o and C32o • Provides six types of 8 kHz framing pulses: F0o, F8o, F16o, F32o, RSP and TSP • Holdover frequency accuracy of 0.025 ppm • Phase slope of 5 ns/125 µs • Attenuates wander from 2.
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