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83023I - Differential-to-LVCMOS Translator/Buffer

Description

The 83023I is a dual, 1-to-1 Differential-to-LVCMOS Translator/Fanout Buffer.The differential inputs can accept most differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and translate into two single-ended LVCMOS outputs.

Features

  • Two LVCMOS / LVTTL outputs.
  • Two differential CLKx, nCLKx input pairs.
  • CLK, nCLK pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL.
  • Maximum output frequency: 350MHz (typical).
  • Output skew: 60ps (maximum).
  • Part-to-part skew: 500ps (maximum).
  • Additive phase jitter, RMS: 0.14ps (typical).
  • Small 8 lead SOIC package saves board space.
  • 3.3V operating supply.
  • -40°C to 85°C.

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Datasheet preview – 83023I

Datasheet Details

Part number 83023I
Manufacturer Renesas Electronics
File Size 288.85 KB
Description Differential-to-LVCMOS Translator/Buffer
Datasheet download datasheet 83023I Datasheet
Additional preview pages of the 83023I datasheet.

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Full PDF Text Transcription

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Dual, 1-TO-1 Differential-to-LVCMOS Translator/Buffer 83023I Data Sheet GENERAL DESCRIPTION The 83023I is a dual, 1-to-1 Differential-to-LVCMOS Translator/Fanout Buffer.The differential inputs can accept most differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and translate into two single-ended LVCMOS outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space. Features • Two LVCMOS / LVTTL outputs • Two differential CLKx, nCLKx input pairs • CLK, nCLK pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 350MHz (typical) • Output skew: 60ps (maximum) • Part-to-part skew: 500ps (maximum) • Additive phase jitter, RMS: 0.
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