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Renesas Electronics Components Datasheet

83052I Datasheet

Single-Ended Multiplexer

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2:1, Single-Ended Multiplexer
83052I
Data Sheet
GENERAL DESCRIPTION
The 83052I is a low skew, 2:1, Single-ended Multiplexer. The 83052I
has two selectable single-ended clock inputs and one single-ended
clock output. The output has a V pin which may be set at 3.3V,
DDO
2.5V, or 1.8V, making the device ideal for use in voltage trans-lation
applications. An output enable pin places the output in a high im-
pedance state which may be useful for testing or debug. The device
operates up to 250MHz and is packaged in an 8 TSSOP.
FEATURES
• 2:1 single-ended multiplexer
• Q nominal output impedance: 15Ω (V = 3.3V)
DDO
• Maximum output frequency: 250MHz
• Propagation delay: 2.7ns (maximum), (V = V = 3.3V)
DD
DDO
• Input skew: 160ps (maximum), (V = V = 3.3V)
DD
DDO
• Part-to-part skew: 490ps (maximum), (V = V = 3.3V)
DD
DDO
Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz):
0.18ps (typical), (V = V = 3.3V)
DD
DDO
• Operating supply modes:
V /V
DD DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
CLK0
CLK1
Q
SEL0
OE
PIN ASSIGNMENT
VDDO 1
GND 2
CLK1 3
VDD 4
8Q
7 SEL0
6 CLK0
5 OE
83052I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
©2015 Integrated Device Technology, Inc
1
December 15, 2015


Renesas Electronics Components Datasheet

83052I Datasheet

Single-Ended Multiplexer

No Preview Available !

83052I Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V
Power
Output supply pin.
DDO
2
GND
Power
Power supply ground.
3, 6
CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
4
V
Power
Positive supply pin.
DD
5
OE
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
7
SEL0
Input
Pulldown
Clock select input. See Table 3. Control Input Function Table.
LVCMOS / LVTTL interface levels.
8
Q
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C
IN
R
PULLUP
R
PULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
C
PD
Power Dissipation Capacitance
(per output)
R
Output Impedance
OUT
Test Conditions
V = 3.465V
DDO
V = 2.625V
DDO
V = 1.89V
DDO
Minimum
Typical
4
51
51
18
19
19
15
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
TABLE 3. CONTROL INPUT FUNCTION TABLE
Control Inputs
Input Selected to Q
SEL0
0
CLK0
1
CLK1
©2015 Integrated Device Technology, Inc
2
December 15, 2015



Part Number 83052I
Description Single-Ended Multiplexer
Maker Renesas
Total Page 3 Pages
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83052I Datasheet PDF





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