900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Renesas Electronics Components Datasheet

8413S09 Datasheet

Clock Generator

No Preview Available !

Clock Generator for Cavium
Processors
8413S09
DATA SHEET
General Description
Features
The 8413S09 is a PLL-based clock generator specifically designed
for the Cavium Networks OCTEON Plus 58xx family of processors
and Advanced Mezzanine Card (AMC) applications. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express, sRIO, XAUI, and SGMII SerDes
reference clocks and the clock for Gigabit Ethernet MACs or PHYs.
The clock generator offers ultra low-jitter, low-skew clock outputs,
and edge rates that easily meet the input requirements for processor
core reference, PCI-Express, sRIO, XAUI, and SGMII SerDes
interfaces. The output frequencies are generated from a 25MHz
external input source or an external 25MHz parallel resonant
crystal.The industrial temperature range of the 8413S09 supports a
variety of communications, networking, processor, DSP, data
acquisition, storage and I/O application requirements.
Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for PCI Express, sRIO, XAUI, SGMII and HCSL interface
levels
Two fix frequency 100MHz clocks (QDx, nQDx) for PCI Express
and HCSL interface levels
One LVCMOS/LVTTL QREF output, 15output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Applications
Systems using Cavium Networks OCTEON Plus 58XX
processors
Advanced Mezzanine Cards
Integrated Control and Data Plane Solutions
Enterprise, Data Center, Edge and Core Networks
Storage Network Appliances
WAN Optimization Appliances
Wired and Wireless Network Security
Web Servers and Exchange Servers
Supply Modes:
Full 3.3V (HSCL and QREF0)
Mix 3.3V core /2.5V (QREF0)
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37
GND 1
36 OE_C
FSEL_A0 2
35 nQC1
FSEL_A1 3
34 QC1
FSEL_B0 4
33 nQC0
FSEL_B1 5
32 QC0
FSEL_C0 6
FSEL_C1 7
VDDA 8
6
31 VDDO_C
30 VDDO_B
29 nQB1
XTAL_IN 9
28 QB1
XTAL_OUT 10
27 nQB0
REF_SEL 11
26 QB0
GND 12
25 OE_B
13 14 15 16 17 18 19 20 21 22 23 24
REVISION B 1/27/15
SLQPP[PP9)4)13DFNDJH
1
©2015 INTEGRATED DEVICE TECHNOLOGY, INC.


Renesas Electronics Components Datasheet

8413S09 Datasheet

Clock Generator

No Preview Available !

8413S09 DATA SHEET
Block Diagram
FSELA [0:1]
Pulldown
2
FSELB [0:1]
Pulldown
2
FSELC [0:1]
Pulldown
2
Clock
Output
Control
Logic
PLL_SEL
REF_SEL
Pullup
Pullup
CLK
Pulldown
nCLK
PU/PD
0
XTAL_IN
XTAL_OUT
OSC
1
IREF
0
PLL
1
nMR
Pullup
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
00 = 100MHz
01 = 125MHz
10 = 156.25MHz
11 = 312.5MHz
100MHz
2
2
Pullup
2
2
Pullup
2
2
Pullup
2
2
Pullup
QA0 , QA1
nQA0, nQA1
OE_A
QB0 , QB1
nQB0, nQB1
OE_B
QC0 , QC1
nQC0, nQC1
OE_C
QD0 , QD1
nQD0, nQD1
OE_D
Pullup
QREF0
OE_REF
CLOCK GENERATOR FOR CAVIUM PROCESSORS
2
REVISION B 1/27/15



Part Number 8413S09
Description Clock Generator
Maker Renesas
Total Page 3 Pages
PDF Download

8413S09 Datasheet PDF





Similar Datasheet

1 8413S09 Clock Generator
Renesas





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy