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873996 - Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

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Renesas

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873996 Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider by Renesas - Datasheet Preview — Datasheet preview – 873996

Datasheet Details

Part number	873996
Manufacturer	Renesas
File Size	503.71 KB
Description	Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider
Datasheet	873996 Datasheet
Additional preview pages of the 873996 datasheet.

Product details

Description

The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase noise devices from IDT.

Features

Six differential 3.3V LVPECL outputs.
Selectable differential clock inputs.
CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
Input clock frequency range: 49MHz to 213.33MHz.
Output clock frequency range: 49MHz to 640MHz.
VCO range: 490MHz to 640MHz.
External feedback for “zero delay” clock regeneration with conﬁgurable frequencies.
Output skew: 100ps (maximum).

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Published: Mar 11, 2024 |