8A34002 Overview
Synchronization Management Unit 8A34002 Datasheet Overview The 8A34002 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL). Optional...
8A34002 Key Features
- Four independent timing channels
- Each can act as a frequency synthesizer, jitter attenuator
- DPLLs generate tele pliant clocks
- pliant with ITU-T G.8262 for Synchronous Ethernet
- pliant with legacy SONET/SDH and PDH
- DPLL Digital Loop Filters (DLFs) are programmable with cut
- DPLL/DCO channels share frequency information using the
- Switching between DPLL and DCO modes is hitless and
- Automatic reference switching between DCO and DPLL
- Generates output frequencies that are independent of input