8P73S674 Description
The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer. The device has been designed for clock signal division and fanout in wireless base station (radio and base band), high-end puting and telemunication equipment. The device is optimized to deliver excellent phase noise performance.
8P73S674 Key Features
- Clock signal division and distribution
- SiGe technology for high-frequency and fast signal rise/fall times
- Four low-skew LVPECL clock outputs
- Supports frequency division of ÷1, ÷2, ÷4 and ÷8
- Maximum Output frequency: 1GHz
- Output skew: 100ps (maximum)
- LVPECL output rise/fall time (20%
- 80%): 220ps (maximum)
- 1.8V core and output supply mode
- Supports 1.8V I/O LVCMOS logic levels for all control pins