Part number:
8S89296
Manufacturer:
File Size:
544.20 KB
Description:
Lvds programmable delay line.
* ▪ One LVDS level output ▪ One differential clock input pair ▪ Differential input clock (IN, nIN) can accept the following signaling levels: LVPECL, LVDS, CML ▪ Maximum frequency: 800MHz ▪ Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps ▪ D[10:0] can accept LVPECL, LVCMOS or LVTTL levels ▪ Fu
8S89296
544.20 KB
Lvds programmable delay line.
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