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8T33FS6111 Datasheet

Low Voltage 2.5V/3.3V Differential LVPECL/HSTL Fanout Buffer

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Low Voltage 2.5V/3.3V Differential
LVPECL/HSTL Fanout Buffer
8T33FS6111
DATA SHEET
General Description
The 8T33FS6111 is a bipolar monolithic differential clock fanout
buffer. Designed for most demanding clock distribution systems, the
8T33FS6111 supports various applications that require distribution
of precisely aligned differential clock signals. Using SiGe:C
technology and a fully differential architecture, the device offers very
low skew outputs and superior digital signal characteristics. Target
applications for this clock driver is high performance clock distribution
in computing, networking and telecommunication systems.
The 8T33FS6111 is designed for low skew clock distribution systems
and supports clock frequencies up to 2.7GHz. The device accepts
two clock sources. The CLKA input can be driven by LVPECL
compatible signals, the CLKB input accepts HSTL or LVPECL
compatible signals. The selected input signal is distributed to 10
identical, LVPECL outputs. If VBB is connected to the CLKA input and
bypassed to GND by a 10nF capacitor, the 8T33FS6111 can be
driven by single-ended LVPECL signals utilizing the VBB bias voltage
output.
In order to meet the tight skew specification of the device, both
outputs of a differential output pair should be terminated, even if only
one output is used. In the case where not all ten outputs are used,
the output pairs on the same package side as the parts being used
on that side should be terminated.
The 8T33FS6111 can be operated from a single 3.3V or 2.5V supply.
Pin Assignment
VCC
CLK_SEL
32 31 30 29 28 27 26 25
1
24
2
23
Q3
nQ3
CLKA 3
22 Q4
nCLKA 4
VBB 5
8T33FS6111
21 nQ4
20 Q5
CLKB 6
19 nQ5
nCLKB 7
18 Q6
VEE 8
17 nQ6
9 10 11 12 13 14 15 16
Features
• 1:10 differential clock distribution
• 28ps typical output skew
• Fully differential architecture from input to all outputs
• SiGe:C technology supports near-zero output skew
• Supports DC to 2.7GHz operation of clock or data signals
• LVPECL compatible differential clock outputs
• LVPECL/HSTL compatible differential clock inputs
• Single 3.3V or 2.5V supply
• Standard 32-Lead VFQFN package
• Standard 32-lead LQFP package
• Standard 32-lead TQFP package with EPAD
• -40°C to 85°C ambient operating temperature
Block Diagram
VCC
CLKA
nCLKA
0
1
VCC
CLKB
nCLKB
CLK_SEL
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
VBB
.
8T33FS6111 REVISION 1 12/02/14
1
©2014 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

8T33FS6111 Datasheet

Low Voltage 2.5V/3.3V Differential LVPECL/HSTL Fanout Buffer

No Preview Available !

8T33FS6111 DATA SHEET
Pin Description and Characteristics
Table 1. Pin Description
Number
Name
1
VCC
2
CLK_SEL
3
CLKA
4
nCLKA
5
VBB
6
CLKB
7
nCLKB
8
VEE
9
VCC
10
nQ9
11
Q9
12
nQ8
13
Q8
14
nQ7
15
Q7
16
VCC
17
nQ6
18
Q6
19
nQ5
20
Q5
21
nQ4
22
Q4
23
nQ3
24
Q3
25
VCC
26
nQ2
27
Q2
28
nQ1
29
Q1
30
nQ0
31
Q0
32
VCC
Power
Input
Input
Input
Output
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Output
Output
Output
Output
Output
Output
Power
Type
Description
Positive power supply. All VCC pins must be connected to the
positive power supply for correct DC and AC operation.
Active clock input select.
LVPECL Differential reference clock signal input.
LVPECL Differential reference clock signal input.
DC
Reference voltage output for single ended LVPECL operation.
HSTL/LVPECL Alternative differential reference clock signal input.
HSTL/LVPECL Alternative differential reference clock signal input.
Negative power supply.
Positive power supply. All VCC pins must be connected to the
positive power supply for correct DC and AC operation.
LVPECL
LVPECL
Differential clock outputs.
LVPECL
LVPECL
Differential clock outputs.
LVPECL
LVPECL
Differential clock outputs.
Positive power supply. All VCC pins must be connected to the
positive power supply for correct DC and AC operation.
LVPECL
LVPECL
Differential clock outputs.
LVPECL
LVPECL
Differential clock outputs.
LVPECL
LVPECL
Differential clock outputs.
LVPECL
LVPECL
Differential clock outputs.
Positive power supply. All VCC pins must be connected to the
positive power supply for correct DC and AC operation.
LVPECL
LVPECL
Differential clock outputs.
LVPECL
LVPECL
Differential clock outputs.
LVPECL
LVPECL
Differential clock outputs.
Positive power supply. All VCC pins must be connected to the
positive power supply for correct DC and AC operation.
Table 2. Function Table
Control
Default
CLK_SEL
0
0
CLKA, nCLKA input pair is active. CLKA can
be driven by LVPECL compatible signals.
1
CLKB, nCLKB input pair is active.
CLKB can be driven by HSTL or LVPECL
compatible signals.
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL
2
FANOUT BUFFER
REVISION 1 12/02/14



Part Number 8T33FS6111
Description Low Voltage 2.5V/3.3V Differential LVPECL/HSTL Fanout Buffer
Maker Renesas
Total Page 3 Pages
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