8T49N241 Datasheet | Renesas

Description The 8T49N241 has one fractional-feedback PLL that can be used as a jitter attenuator and frequency translator. It is equipped with one integer and three fractional output dividers, allowing the generation of up to four different output frequencies, ranging from 8k Hz to 1GHz. These frequencies are pletely independent of each other, the input reference frequencies, and the crystal reference frequency. The device places virtually no constraints on input to output frequency conversion, supporting all FEC rates, including the new revision of ITU-T Remendation G.709 (2009), most with 0ppm conversion error. The outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels. This makes it ideal to be used in any frequency synthesis application, including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates. The 8T49N241 accepts up to two differential or single-ended input clocks and a fundamental-mode crystal input. The internal PLL can lock to either of the input reference clocks or just to the crystal to behave as a frequency synthesizer. The PLL can use the second input for redundant backup of the primary input reference, but in this case, both input clock references must be related in frequency. The device supports hitless reference switching between input clocks. The device monitors both input clocks for Loss of Signal (LOS), and generates an alarm when an input clock failure is detected. Automatic and manual hitless reference switching options are supported. LOS behavior can be set to support gapped or un-gapped clocks. The 8T49N241 supports holdover. The holdover has an initial accuracy of ±50pp B from the point where the loss of all applicable input reference(s) has been detected. It maintains a historical average operating point for the PLL that may be returned to in holdover at a limited phase slope. The PLL has a register-selectable loop bandwidth from 0.2Hz to 6.4k Hz. The device supports Output...