8T49N287 Datasheet | Renesas

Description The 8T49N287 has two independent, fractional-feedback PLLs that can be used as jitter attenuators and frequency translators. It is equipped with six integer and two fractional output dividers, allowing the generation of up to 8 different output frequencies, ranging from 8k Hz to 1GHz. Four of these frequencies are pletely independent of each other and the inputs. The other four are related frequencies. The eight outputs may select among LVPECL, LVDS, HCSL, or LVCMOS output levels. This makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates. The device may also behave as a frequency synthesizer. The 8T49N287 accepts up to two differential or single-ended input clocks and a crystal input. Each of the two internal PLLs can lock to different input clocks which may be of independent frequencies. Each PLL can use the other input for redundant backup of the primary clock, but in this case, both input clocks must be related in frequency. The device supports hitless reference switching between input clocks. The device monitors all input clocks for Loss of Signal (LOS), and generates an alarm when an input clock failure is detected. Automatic and manual hitless reference switching options are supported. LOS behavior can be set to support gapped or un-gapped clocks. The 8T49N287 supports holdover for each PLL. The holdover has an initial accuracy of ±50pp B from the point where the loss of all applicable input reference(s) has been detected. It maintains a historical average operating point for each PLL that may be returned to in holdover at a limited phase slope. The device places no constraints on input to output frequency conversion, supporting all FEC rates, including the new revision of ITU-T Remendation G.709 (2009), most with 0ppm conversion error. Each PLL has a register-selectable loop bandwidth from 1.4Hz to 360Hz. Each output...