Datasheet4U.com

8T73S208B-01 - Differential LVPECL Clock Divider and Fanout Buffer

Renesas

📥 Download Datasheet

8T73S208B-01 Datasheet Preview — Preview of 8T73S208B-01 PDF

datasheet Preview Page 2

datasheet Preview Page 3

Datasheet Details

Part number	8T73S208B-01
Manufacturer	Renesas ↗
File Size	559.66 KB
Description	Differential LVPECL Clock Divider and Fanout Buffer
Datasheet	8T73S208B-01-Renesas.pdf

8T73S208B-01 Product details

Description

The 8T73S208B-01 is a high-performance differential LVPECL clock divider and fanout buffer.

Features

One differential input reference clock.
Differential pair can accept the following differential input levels: LVDS, LVPECL, CML.
Integrated input termination resistors.
Eight LVPECL outputs.
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8.
Maximum input clock frequency: 1GHz.
LVCMOS interface levels for the control inputs.
Individual output enable/disabled by I2C interface.
Power-up state: all outputs disa.

📁 8T73S208B-01 Similar Datasheet

8T73S208 - Differential LVPECL Clock Divider and Fanout Buffer (Integrated Device Technology)
8T73S208A-01 - LVPECL Clock Divider and Buffer (IDT)
8T74S208 - 2.5V Differential LVDS Clock Divider and Fanout Buffer (IDT)
8T74S208A-01 - 2.5V Differential LVDS Clock Divider and Fanout Buffer (IDT)
8T74S208C-01 - 2.5 V Differential LVDS Clock Divider and Fanout Buffer (IDT)
8T79S308 - 1:8 Universal Differential Fanout Buffer (IDT)

Other Datasheets by Renesas

8T73S1802 - 1:2 Clock Fanout Buffer and Frequency Divider
8T74S208B - LVDS Clock Divider and Fanout Buffer

Published: Jun 4, 2020 |