8V19N472 Datasheet | Renesas

Femto Clock® NG Jitter Attenuator and Clock Synthesizer Description The 8V19N472 is a fully integrated Femto Clock NG Jitter Attenuator and Clock Synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency. This PLL has two VCO circuits at 2949.12MHz and 2400- 2500MHz, respectively, for enhanced frequency flexibility. The device generates the output clock signals from the selected VCO by frequency division. Five independent frequency dividers are available, four support integer-divider ratios and one integer as well as fractional-divider ratios. Delay circuits can be used for achieving alignment and controlled phase delay between clock signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The 8V19N472 is configured through an SPI interface and reports lock and signal loss status in internal registers and via a lock detect (LOCK) output. Internal status bit changes can also be reported via the n INT output. The device is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications. The device is a member of the high-performance clock family from IDT. Typical Applications - Low-phase noise clock generation, specifically for jitter-sensitive...