• Part: 9DBL0442
  • Description: 3.3V PCIe Zero Delay Buffer
  • Manufacturer: Renesas
  • Size: 401.12 KB
Download 9DBL0442 Datasheet PDF
Renesas
9DBL0442
Description The 9DBL0442 / 9DBL0452 devices are 3.3V members of Renesas’ Full-Featured PCIe family. The 9DBL0442 / 9DBL0452 supports PCIe Gen1- 4 mon Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL04P2 can be factory programmed with a user-defined power up default SMBus configuration. Typical Application PCIe Gen1- 4 clock distribution for Riser Cards, Storage, Networking, JBOD, munications, Access Points Output Features - Four 1- 200 MHz Low-Power HCSL (LP-HCSL) DIF pairs - 9DBL0442 default ZOUT = 100Ω - 9DBL0452 default ZOUT = 85Ω - 9DBL04P2 factory programmable defaults - Easy AC-coupling to other logic families, see Renesas application note AN-891 Key Specifications - PCIe Gen1- 4 CC pliant in ZDB mode - PCIe Gen2 SRIS pliant in ZDB mode - Supports PCIe Gen2- 3 SRIS in fanout mode - DIF cycle-to-cycle jitter < 50ps - DIF output-to-outpu...