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9DBL0442 - 3.3V PCIe Zero Delay Buffer

General Description

The 9DBL0442 / 9DBL0452 devices are 3.3V members of Renesas’ Full-Featured PCIe family.

4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems.

Key Features

  • Four 1.
  • 200 MHz Low-Power HCSL (LP-HCSL) DIF pairs.
  • 9DBL0442 default ZOUT = 100Ω.
  • 9DBL0452 default ZOUT = 85Ω.
  • 9DBL04P2 factory programmable defaults.
  • Easy AC-coupling to other logic families, see Renesas.

📥 Download Datasheet

Datasheet Details

Part number 9DBL0442
Manufacturer Renesas
File Size 401.12 KB
Description 3.3V PCIe Zero Delay Buffer
Datasheet download datasheet 9DBL0442 Datasheet

Full PDF Text Transcription for 9DBL0442 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 9DBL0442. For precise diagrams, and layout, please refer to the original PDF.

4-Output 3.3V PCIe Zero Delay Buffer 9DBL0442 / 9DBL0452 Datasheet Description The 9DBL0442 / 9DBL0452 devices are 3.3V members of Renesas’ Full-Featured PCIe family. The...

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52 devices are 3.3V members of Renesas’ Full-Featured PCIe family. The 9DBL0442 / 9DBL0452 supports PCIe Gen1–4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL04P2 can be factory programmed with a user-defined power up default SMBus configuration.

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