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9DBL0452 - 3.3V PCIe Zero Delay Buffer

This page provides the datasheet information for the 9DBL0452, a member of the 9DBL0442 3.3V PCIe Zero Delay Buffer family.

Description

The 9DBL0442 / 9DBL0452 devices are 3.3V members of Renesas’ Full-Featured PCIe family.

4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems.

Features

  • Four 1.
  • 200 MHz Low-Power HCSL (LP-HCSL) DIF pairs.
  • 9DBL0442 default ZOUT = 100Ω.
  • 9DBL0452 default ZOUT = 85Ω.
  • 9DBL04P2 factory programmable defaults.
  • Easy AC-coupling to other logic families, see Renesas.

📥 Download Datasheet

Datasheet preview – 9DBL0452

Datasheet Details

Part number 9DBL0452
Manufacturer Renesas
File Size 401.12 KB
Description 3.3V PCIe Zero Delay Buffer
Datasheet download datasheet 9DBL0452 Datasheet
Additional preview pages of the 9DBL0452 datasheet.

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Other Datasheets by Renesas
  • 9DBL0452 - Zero-Delay/Fanout Buffer
  • 9DBL0452C - 2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers
  • 9DBL0455 - 2 and 4-Output 3.3V PCIe Gen1-5 Clock Fanout Buffers
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  • 9DBL0242 - Zero-Delay/Fanout Buffer
  • 9DBL0242C - 2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers

Full PDF Text Transcription

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4-Output 3.3V PCIe Zero Delay Buffer 9DBL0442 / 9DBL0452 Datasheet Description The 9DBL0442 / 9DBL0452 devices are 3.3V members of Renesas’ Full-Featured PCIe family. The 9DBL0442 / 9DBL0452 supports PCIe Gen1–4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL04P2 can be factory programmed with a user-defined power up default SMBus configuration.
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