9DBL0452 Key Features
- Four 1-200 MHz Low-Power HCSL (LP-HCSL) DIF pairs
- 9DBL0442 default ZOUT = 100Ω
- 9DBL0452 default ZOUT = 85Ω
- 9DBL04P2 factory programmable defaults
- Easy AC-coupling to other logic families, see Renesas application note AN-891
- PCIe Gen1-4 CC pliant in ZDB mode
- PCIe Gen2 SRIS pliant in ZDB mode
- Supports PCIe Gen2-3 SRIS in fanout mode
- DIF cycle-to-cycle jitter < 50ps
- DIF output-to-output skew < 50ps
