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9DBL0452 Datasheet 3.3V PCIe Zero Delay Buffer

Manufacturer: Renesas

Overview: 4-Output 3.3V PCIe Zero Delay Buffer 9DBL0442 / 9DBL0452 Datasheet.

Download the 9DBL0452 datasheet PDF. This datasheet also includes the 9DBL0442 variant, as both parts are published together in a single manufacturer document.

General Description

The 9DBL0442 / 9DBL0452 devices are 3.3V members of Renesas’ Full-Featured PCIe family.

The 9DBL0442 / 9DBL0452 supports PCIe Gen1–4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems.

It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines.

Key Features

  • Four 1.
  • 200 MHz Low-Power HCSL (LP-HCSL) DIF pairs.
  • 9DBL0442 default ZOUT = 100Ω.
  • 9DBL0452 default ZOUT = 85Ω.
  • 9DBL04P2 factory programmable defaults.
  • Easy AC-coupling to other logic families, see Renesas.