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Renesas Electronics Components Datasheet

9DBL0452 Datasheet

3.3V PCIe Zero Delay Buffer

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4-Output 3.3V PCIe Zero Delay
Buffer
9DBL0442 / 9DBL0452
Datasheet
Description
The 9DBL0442 / 9DBL0452 devices are 3.3V members of
Renesas’ Full-Featured PCIe family. The 9DBL0442 / 9DBL0452
supports PCIe Gen1–4 Common Clocked (CC) and PCIe
Separate Reference Independent Spread (SRIS) systems. It
offers a choice of integrated output terminations providing direct
connection to 85or 100transmission lines. The 9DBL04P2 can
be factory programmed with a user-defined power up default
SMBus configuration.
Typical Application
PCIe Gen1–4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
Four 1–200 MHz Low-Power HCSL (LP-HCSL) DIF pairs
• 9DBL0442 default ZOUT = 100
• 9DBL0452 default ZOUT = 85
• 9DBL04P2 factory programmable defaults
Easy AC-coupling to other logic families, see Renesas
application note AN-891
Key Specifications
PCIe Gen1–4 CC compliant in ZDB mode
PCIe Gen2 SRIS compliant in ZDB mode
Supports PCIe Gen2–3 SRIS in fanout mode
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for PCIe
Bypass mode additive phase jitter 160fs rms typical at
156.25MHz (1.5MHz to 10MHz)
Features
Direct connection to 100(xx42) or 85(xx52) transmission
lines; saves 16 resistors compared to standard PCIe devices
132mW typical power consumption in PLL mode; eliminates
thermal concerns
SMBus-selectable features allows optimization to customer
requirements:
• Control input polarity
• Control input pull up/downs
• Slew rate for each output
• Differential output amplitude
• Output impedance for each output
• 50, 100, 125 MHz operating frequency
Customer defined SMBus power up default can be
programmed into P2 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by common
clock sources
Spread Spectrum tolerant; allows reduction of EMI
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
5 × 5 mm 32-VFQFPN package; minimal board space
Block Diagram
vOE(3:0)#
CLK_IN
CLK_IN#
vSADR_tri
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
4
SS Compatible
PLL
DIF3
DIF2
DIF1
DIF0
Note: Resistors default to internal on xx42/xx52 devices. P2 devices have programmable default impedances on an output-by-output basis.
©2020 Renesas Electronics Corporation
1
February 28, 2020


Renesas Electronics Components Datasheet

9DBL0452 Datasheet

3.3V PCIe Zero Delay Buffer

No Preview Available !

9DBL0442 / 9DBL0452 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Alternate Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics–Clock Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics–SMBus Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics–Input/Supply/Common Parameters – Normal Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics–DIF Low-Power HCSL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics–Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics–Filtered Phase Jitter Parameters – PCIe Common Clocked (CC) Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics–Filtered Phase Jitter Parameters – PCIe Separate Reference Independent Spread (SRIS) Architectures . . . . . . . 11
Electrical Characteristics–Unfiltered Phase Jitter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
©2020 Renesas Electronics Corporation
2
February 28, 2020


Part Number 9DBL0452
Description 3.3V PCIe Zero Delay Buffer
Maker Renesas
PDF Download

9DBL0452 Datasheet PDF





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