9DBL0452 Features
* ▪ Four 1
* 200 MHz Low-Power HCSL (LP-HCSL) DIF pairs
* 9DBL0442 default ZOUT = 100Ω
* 9DBL0452 default ZOUT = 85Ω
* 9DBL04P2 factory programmable defaults ▪ Easy AC-coupling to other logic families, see Renesas application note AN-891 Key Specifications ▪ PCIe Gen1
Datasheet Details
9DBL0452, 9DBL0442
401.12 KB
3.3v pcie zero delay buffer.
This datasheet PDF includes multiple part numbers: 9DBL0452, 9DBL0442.
Please refer to the document for exact specifications by model.
📁 Related Datasheet
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9DBL0453 4-output 3.3V LP-HCSL Zero-Delay Buffer (IDT)
9DBL0455 2 and 4-Output 3.3V PCIe Gen1-5 Clock Fanout Buffers (Renesas)
9DBL0455 PCIe Gen1-5 Clock Fanout Buffers (IDT)
9DBL04 4-output 3.3V PCIe Zero-delay Buffer (IDT)
9DBL0442 3.3V PCIe Zero Delay Buffer (Renesas)
9DBL0452 Distributor
