9DBL0853 Overview
The 9DBL08x3 devices are 3.3V members of IDT's Full-Featured PCIe clock family. They support PCIe Gen1-4 mon Clock (CC) architectures and also support NVLINK applications. The 9DBL08x3 parts have a Loss of Signal (LOS) indicator to support fault-tolerant, high reliability systems.
9DBL0853 Key Features
- Loss Of Signal (LOS) open drain output
- 1-200 MHz Low-Power (LP) HCSL DIF pairs
- 9DBL0843 default Zout = 100Ω
- 9DBL0853 default Zout = 85Ω
- Easy AC-coupling to other logic families, see IDT application note AN-891
- PCIe Gen1-4 CC pliant in ZDB or fanout buffer mode
- Supports NVLINK at 156.25M in ZDB or fanout buffer mode
- DIF cycle-to-cycle jitter <50ps
- DIF output-to-output skew < 50ps
- Bypass mode additive phase jitter is 0 ps typical rms for PCIe
