9DBL0853 Datasheet | Renesas

8-output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator 9DBL08x3 Datasheet General Description The 9DBL08x3 devices are 3.3V members of IDT's Full-Featured PCIe clock family. They support PCIe Gen1-4 mon Clock (CC) architectures and also support NVLINK applications. The 9DBL08x3 parts have a Loss of Signal (LOS) indicator to support fault-tolerant, high reliability systems. Remended Application PCIe Gen1-4 and NVLINK clock distribution for Riser Cards, Storage, Networking, JBOD, munications, Access Points Output Features - Loss Of Signal (LOS) open drain output - 8 - 1-200 MHz Low-Power (LP) HCSL DIF pairs - 9DBL0843 default Zout = 100Ω - 9DBL0853 default Zout = 85Ω - Easy AC-coupling to other logic families, see IDT application note AN-891. Key Specifications - PCIe Gen1-4 CC pliant in ZDB or fanout buffer mode - Supports NVLINK at 156.25M in ZDB or fanout buffer mode - DIF cycle-to-cycle jitter <50ps - DIF output-to-output skew < 50ps - Bypass mode additive phase jitter is 0 ps typical rms for PCIe - Bypass mode additive phase jitter 160fs rms typ. @ 156.25M (1.5M to 10M) Block Diagram vOE(7:0)# 7 Features /Benefits - LOS indicator signals loss of input clock; adds fault tolerance, eases system diagnostics - Direct connection to 100Ω (xx43) or 85Ω (xx53) transmission lines; saves 32 resistors pared to standard PCIe devices - 205mW typical power consumption (PLL mode@3.3V); eliminates thermal concerns - VDDIO allows >33% power savings at optional 1.05V; maximum power savings...