9DBV0841 Datasheet | Renesas

8-Output 1.8V PCIe ZDB Gen1- 3, PCIe Gen1- 4 Buffer with Zo = 100ohms Description The 9DBV0841 is a 1.8V member of IDT's full featured PCIe family. It has integrated output terminations providing Zo = 100 for direct connection for 100 transmission lines. The device has 8 output enables for clock management and 3 selectable SMBus addresses. Typical Applications - SSD, micro Servers, WLAN Access points Output Features - Eight 1- 200MHz Low-Power (LP) HCSL DIF pairs Key Specifications - DIF cycle-to-cycle jitter < 50ps - DIF output-to-output skew < 50ps - DIF additive phase jitter is < 100fs rms for PCIe Gen4 - DIF additive phase jitter < 300fs rms for 12k Hz- 20MHz Block Diagram Features /Benefits - LP-HCSL outputs save 32 resistors; minimal board space and BOM cost - 62m W typical power consumption in PLL mode; eliminates thermal concerns - Spread Spectrum (SS) patible; allows use of SS for EMI reduction - OE# pins; support DIF power management - HCSL patible differential input; can be driven by mon clock sources - Programmable Slew rate for each output; allows tuning for various line lengths - Programmable output amplitude; allows tuning for various application environments - Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application - Outputs blocked until PLL is locked; clean system start-up - Software selectable 50MHz or 125MHz PLL operation; useful for Ethernet applications - Configuration can be acplished with strapping pins; SMBus interface not required for device control - 3.3V tolerant SMBus interface works with legacy controllers - Space saving 6 × 6 mm 48-VFQFPN; minimal board...