9DBV0841 Key Features
- Eight 1-200MHz Low-Power (LP) HCSL DIF pairs
- DIF cycle-to-cycle jitter < 50ps
- DIF output-to-output skew < 50ps
- DIF additive phase jitter is < 100fs rms for PCIe Gen4
- DIF additive phase jitter < 300fs rms for 12kHz-20MHz
- LP-HCSL outputs save 32 resistors; minimal board space
- 62mW typical power consumption in PLL mode; eliminates
- OE# pins; support DIF power management
- HCSL patible differential input; can be driven by
- Programmable output amplitude; allows tuning for various
