9DML0451 Key Features
- Four 1-200MHz Low-Power HCSL (LP-HCSL) DIF pairs
- 9DML0441 default ZOUT = 100
- 9DML0451 default ZOUT = 85
- See AN-891 for easy termination to other logic levels
- Direct connection to 100 (xx41) or 85 (xx51)
- 79mW typical power consumption
- Spread Spectrum Clocking (SSC) patible
- OE# pins for each output
- HCSL-patible differential inputs
- Selectable asynchronous or glitch-free, gapped-clock
