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9FGV1002C Datasheet

PCIe Gen1-5 Low-Power PhiClock Generators

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PCIe Gen1–5 Low-Power
Programmable PhiClock™
Generators
9FGV1002C / 9FGV1006C
Datasheet
Description
The 9FGV1002C / 9FGV1006C are members of the Renesas
PhiClock™ programmable clock generator family. These devices
are optimized for low phase noise spread-spectrum applications
such as PCIe Express. The 9FGV1002C is a four-output device
while the 9FGV1006C is a smaller two-output version. Four
user-defined configurations may be selected via two hardware
select pins or two I2C bits, allowing easy software selection of the
desired configuration. Any one of the four OTP configurations may
be specified as the default when operating in I2C mode. Four
unique I2C addresses are available, allowing easy I2C access to
multiple components.
Typical Applications
High-performance Computing (HPC)
Enterprise Storage including eSSDs
10G / 25G / 100G Ethernet
Fiber Optic Modules
NVLink
PCIe Clocking Architectures
Common Clocked (CC)
Independent Reference without spread spectrum (SRnS)
Independent Reference with spread spectrum (SRIS)
Output Features
9FGV1002: 4 programmable output pairs plus 2 LVCMOS REF
outputs
9FGV1006: 2 programmable output pairs plus 1 LVCMOS REF
output
1 integer, fractional or spread spectrum output frequency per
configuration
1MHz–325MHz LVDS or LP-HCSL outputs
Features
1.8V to 3.3V power supplies
Individual 1.8V to 3.3V VDDO for each output pair
Supports HCSL, LVDS and LVCMOS I/O standards
HCSL utilizes Renesas’ LP-HCSL technology for improved
performance, lower power and higher integration:
Programmable output impedance of 85Ω or 100Ω
Supports LVPECL and CML logic with easy AC coupling – see
application note AN-891 for alternate terminations
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I2C
Internal crystal load capacitors
< 125mW at 1.8V with LP-HCSL outputs at 100MHz
(9FGV1002C)
< 100mW at 1.8V with LP-HCSL outputs at 100MHz
(9FGV1006C)
4 programmable I2C addresses: D0, D2, D4, D6
Easily configured with Renesas Timing Commander™ software
or Web Configuration tool
4 × 4 mm 24-VFQFPN with integrated crystal option
(9FGV1002CQ)
3 × 3 mm 16-LGA with integrated crystal option
(9FGV1006CQ)
Programmable spread spectrum modulation frequency and
amount
Key Specifications
12kHz–20MHz typical phase jitter at 156.25M (SSC off) 276ps
RMS
PCIe Gen4 jitter (CC) < 0.23ps RMS
PCIe Gen5 jitter (CC) < 0.08ps RMS
PCIe Gen5 jitter (SRIS) < 0.07ps RMS
©2020 Renesas Electronics Corporation
1
November 30, 2020


Renesas Electronics Components Datasheet

9FGV1002C Datasheet

PCIe Gen1-5 Low-Power PhiClock Generators

No Preview Available !

9FGV1002C / 9FGV1006C Datasheet
9FGV1002C / 9FGV1006C Block Diagram
Consult factory if design requires REF1.
XIN/CLKIN
XO
OSC
9FGV1002CQ and
9FGV1006CQ integrate the
crystal
Prog.
Output
vSEL0/SCL
vSEL1/SDA
9FGV1002
^OEB
^OEA
Prog.
FRAC PLL
INT
Output
(SSC)
DIV
SMBus Factory
Engine Configuration
Prog.
Output
Control
Logic
Prog.
Output
VDDREFp
REF1
9FGV1002
vREF0_SEL_I2C#
O UT 3#
O UT 3
VDDO3
O UT 2#
O UT 2
VDDO2
9FGV1002
O UT 1#
O UT 1
VDDO1
OUT0#
O UT 0
VDDO0
Table 1. OE Mapping
OE[B:A]
00
01
10
11
OUT0
Running
Running
Running
Running
OUT1
Stopped
Running
Running
Running
OUT2
Stopped
Stopped
Running
Running
OUT3
Stopped
Stopped
Stopped
Running
REF0
Running
Running
Running
Running
REF1
Running
Running
Running
Running
©2020 Renesas Electronics Corporation
2
November 30, 2020


Part Number 9FGV1002C
Description PCIe Gen1-5 Low-Power PhiClock Generators
Maker Renesas
PDF Download

9FGV1002C Datasheet PDF






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