9SBV0802 Datasheet - Renesas

Dual 1:4 Fanout Buffer

9SBV0802 Features

* Eight 1

* 48MHz 1.05V LVCMOS outputs Key Specifications

* Additive cycle-to-cycle jitter < 8ps

* Output-to-output skew within a bank < 50ps

* Output-to-output skew between banks < 100ps Block Diagram vOE_07# vOE_2345# ICLKA_1.05 ICLKB_1.05 VREF_1.05 vOE_16

9SBV0802 General Description

The 9SBV0802 provides two banks of four 1.05V LVCMOS outputs. Each bank has its own input. There are three OE pins. Two OE pins control two outputs each and one OE pin controls four outputs. One 9SBV0802 allows one PCH to easily support four CPUs with point to point routing of the PM signals. Two 9S.

9SBV0802 Datasheet (583.81 KB)