9ZXL0651 Datasheet | Renesas

Description The 9ZXL0651 is a low-power 6-output differential buffer that meets all the performance requirements of the Intel DB1200Z specification. It consumes 50% less power than standard HCSL devices and has internal terminations to allow direct connection to 85 transmission lines. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications. Applications Buffer for Romley, Grantley and Purley Servers, SSDs and PCIe Output Features - 6 - LP-HCSL Output Pairs w/integrated terminations (Zo = 85) Block Diagram Features - 25MHz PFT clock delay management - Low-Power-HCSL outputs with Zo = 85; save power and board space - no termination resistors required. Ideal for blade servers. - Space-saving 40-pin VFQFPN package - Fixed feedback path for 0ps input-to-output delay - 6 OE# pins; hardware control of each output - PLL or bypass mode; PLL can dejitter ining clock - Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs - Spread spectrum patible; tracks spreading input clock for low EMI Key Specifications - Cycle-to-cycle jitter < 50ps - Output-to-output skew < 65ps - Input-to-output delay variation < 50ps - PCIe Gen3 phase jitter < 1.0ps RMS - QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS OE(5:0)# DIF_IN DIF_IN# HIBW_BYPM_LOBW# CKPWRGD/PD# SMBDAT SMBCLK Logic Z-PLL (SS patible) DFB_OUT_NC DIF(5:0) ©2021 Renesas Electronics Corporation January 28, 2021 Pin Configuration NC VDD v OE5# DIF_5# DIF_5 VDD DIF_4# DIF_4 v OE4# VDD 40 39 38 37 36 35 34 33 32 31 VDDA 1 30...