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Renesas Electronics Components Datasheet

9ZXL1950 Datasheet

Low-Power Derivative

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19-Output DB1900Z Low-Power Derivative
with 85ohm Terminations
9ZXL1950
DATASHEET
General Description
The 9ZXL1950 is a DB1900Z derivative buffer utilizing
Low-Power HCSL (LP-HCSL) outputs to increase edge rates
on long traces, reduce board space, and reduce power
consumption more than 50% from the original 9ZX21901.It is
pin-compatible to the 9ZXL1930 and fully integrates the
output terminations. It is suitable for PCI-Express Gen1/2/3 or
QPI/UPI applications, and uses a fixed external feedback to
maintain low drift for demanding QPI/UPI applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers
Output Features
19 LP-HCSL output pairs w/integrated terminations (Zo =
85
Key Specifications
Cycle-to-cycle jitter: <50ps
Output-to-output skew: <50ps
Input-to-output delay variation: <50ps
Phase jitter: PCIe Gen3 <1ps rms
Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms
Features/Benefits
LP-HCSL outputs; up to 90% IO power reduction, better
signal integrity over long traces
Direct connect to 85transmission lines; eliminates 76
termination resistors, saves 130mm2 area
Pin compatible to the 9ZXL1930; easy upgrade to reduced
board space
72-pin VFQFPN package; smallest 19-output Z-buffer
Fixed feedback path; ~0ps input-to-output delay
9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
Separate VDDIO for outputs; allows maximum power
savings
PLL or bypass mode; PLL can dejitter incoming clock
100MHz & 133.33MHz PLL mode; legacy QPI support
Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
Spread spectrum compatible; tracks spreading input clock
for EMI reduction
SMBus Interface; unused outputs can be disabled
Block Diagram
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
FBOUT_NC
DIF(18:0)
9ZXL1950 MAY 11, 2017
1
©2017 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

9ZXL1950 Datasheet

Low-Power Derivative

No Preview Available !

9ZXL1950 DATASHEET
Pin Configuration
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDDA 1
54 DIF12#
GNDA 2
53 DIF12
^100M_133M# 3
52 VDDIO
^vHIBW_BYPM_LOBW# 4
51 GND
CKPWRGD_PD# 5
50 DIF11#
GND 6
49 DIF11
VDDR 7
48 DIF10#
DIF_IN 8
DIF_IN# 9
^SADR0_tri 10
SMBDAT 11
9ZXL1950
(epad should be connected to GND and is
pin 73)
47 DIF10
46 GND
45 VDD
44 DIF9#
SMBCLK 12
43 DIF9
^SADR1_tri 13
42 DIF8#
FBOUT_NC# 14
41 DIF8
FBOUT_NC 15
40 VDDIO
GND 16
39 GND
N/A 1530
DIF0 17
DIF0# 18
38 DIF7#
37 DIF7
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldowm
Pins with ^v prefix have internal 120K pullup/pulldown (biased to VDD/2)
Power Management Table
Inputs
CKPWRGD_PD#
0
1
DIF_IN/
DIF_IN#
X
Running
Control Bits
Outputs
SMBus
EN bit
X
0
1
DIFx/ FBOUT_NC/
DIFx# FB_OUT_NC#
Low/Low
Low/Low
Low/Low
Running
Running Running
PLL State
OFF
ON
ON
Power Connections
VDD
1
7
28, 45, 64
Pin Number
VDDIO
GND
2
6
21, 33, 40,
52, 57, 69
16, 22, 27, 34,
39, 46, 51, 58,
63, 70, 73
Description
Analog PLL
Analog Input
DIF clocks
Functionality at Power-up (PLL mode)
100M_133M#
1
0
DIF_IN
(MHz)
100.00
133.33
DIFx
(MHz)
DIF_IN
DIF_IN
PLL Operating Mode
HiBW_BypM_LoBW# Byte0, bit (7:6)
Low ( PLL Low BW)
00
Mid (Bypass)
01
High (PLL High BW)
11
NOTE: PLL is off in Bypass mode
Tri-level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.2V
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE WITH 85OHM TERMINATIONS2
MAY 11, 2017



Part Number 9ZXL1950
Description Low-Power Derivative
Maker Renesas
Total Page 3 Pages
PDF Download

9ZXL1950 Datasheet PDF





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