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Renesas Electronics Components Datasheet

CD4017BMS Datasheet

CMOS Counter/Dividers

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CD4017BMS, CD4022BMS
CMOS Counter/Dividers
CD4017BMS - Decade Counter with 10 Decoded Outputs
CD4022BMS - Octal Counter with 8 Decoded Outputs
CD4017BMS and CD4022BMS are 5-stage and 4-stage John-
son counters having 10 and 8 decoded outputs, respectively.
Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT sig-
nal. Schmitt trigger action in the CLOCK input circuit provides
pulse shaping that allows unlimited clock input pulse rise and fall
times.
These counters are advanced one count at the positive clock sig-
nal transition if the CLOCK INHIBIT signal is low. Counter
advancement via the clock line is inhibited when the CLOCK
INHIBIT signal is high. A high RESET signal clears the counter to
its zero count. Use of the Johnson counter configuration permits
high speed operation, 2-input decode gating and spike-free
decoded outputs. Anti-lock gating is provided, thus assuring
proper counter sequence. The decoded output are normally low
and go high only at their respective decoded time slot. Each
decoded output remains high for one full clock cycle. A CARRY-
OUT signal completes one cycle every 10 clock input cycles in
the CD4017BMS or every 8 clock input cycles in the
CD4022BMS and is used to ripple-clock the succeeding device
in a multi-device counting chain.
The CD4017BMS and CD4022BMS series types are supplied in
these 16 lead outline packages
Braze Seal DIP
*H4W †H4X
Frit Seal DIP
*H1F †H1E
Ceramic Flatpack
H6W
*CD4017B Only † CD4022B Only
Functional Diagrams
CD4017BMS
CLOCK
CLOCK INHIBIT
RESET
VCC = 16
VSS = 8
14 3 “0”
13 2 “1”
15 4 “2”
7 “3” DECODED
10 “4” DECIMAL
1 “5” OUT
5 “6”
6 “7”
9 “8”
11 “9”
12 CARRY OUT
CD4022BMS
CLOCK
CLOCK INHIBIT
RESET
14
13
15
VCC = 16
VSS = 8
2 “0”
1 “1”
3
7
11
“2”
“3” DECODED
“4” OUT
4 “5”
5 “6”
10 “7”
12 CARRY OUT
FN3297 Rev 0.00
August 1998
DATASHEET
FN3297
Rev 0.00
August 1998
Features
• High Voltage Types (20V Rating)
• Fully Static Operation
• Medium-Speed Operation 10MHz (Typ) at VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
Number 13A, “Standard Specifications for Description
of ‘B’ Series CMOS Devices”
Applications
• Decade Counter/Decimal Decode Display (CD4017BMS)
• Binary Counter/Decoder
• Frequency Division
• Counter Control/Timers
• Divide-by-N Counting
• For Further Application Information, See ICAN-6166
“COS/MOS MSI Counter and Register Design and
Applications”
Pinouts
CD4017BMS
TOP VIEW
NC = NO
CONNECTION
51
12
03
24
65
76
37
VSS 8
16 VDD
15 RESET
14 CLOCK
13 CLOCK INHIBIT
12 CARRY OUT
11 9
10 4
98
CD4022BMS
TOP VIEW
NC = NO
CONNECTION
11
02
23
54
65
NC 6
37
VSS 8
16 VDD
15 RESET
14 CLOCK
13 CLOCK INHIBIT
12 CARRY OUT
11 4
10 7
9 NC
Page 1 of 10


Renesas Electronics Components Datasheet

CD4017BMS Datasheet

CMOS Counter/Dividers

No Preview Available !

CD4017BMS, CD4022BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input  10mA
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . .+265oC
At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance. . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . .
80oCja/W
20oCjc/W
Flatpack Package. . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . .500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . .100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Input Leakage Current
Input Leakage Current
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
SYMBOL
CONDITIONS (NOTE 1)
IDD VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
IIL VIN = VDD or GND VDD = 20
VDD = 18V
IIH VIN = VDD or GND VDD = 20
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VIL
VDD = 18V
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10A
VSS = 0V, IDD = 10A
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
GROUP A
SUBGROUPS
1
2
3
1
2
3
1
2
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
TEMPERATURE
+25oC
+125oC
-55oC
+25oC
+125oC
-55oC
+25oC
+125oC
-55oC
+25oC, +125oC, -55oC
+25oC, +125oC, -55oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+125oC
-55oC
+25oC, +125oC, -55oC
LIMITS
MIN MAX
- 10
- 1000
- 10
-100
-
-1000
-
-100
-
- 100
- 1000
- 100
- 50
14.95
-
0.53 -
1.4 -
3.5 -
- -0.53
- -1.8
- -1.4
- -3.5
-2.8 -0.7
0.7 2.8
VOH > VOL <
VDD/2 VDD/2
- 1.5
UNITS
A
A
A
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
1, 2, 3
+25oC, +125oC, -55oC 3.5
-
V
1, 2, 3
+25oC, +125oC, -55oC -
4V
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being im- 3. For accuracy, voltage is measured differentially to VDD. Limit is
plemented.
0.050V max.
2. Go/No Go test with limits applied to inputs
FN3297 Rev 0.00
August 1998
Page 2 of 10


Part Number CD4017BMS
Description CMOS Counter/Dividers
Maker Renesas
Total Page 10 Pages
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