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EL4584 Key Features

  • 36MHz, general purpose PLL
  • 4FSC based timing (use the EL4585 for 8FSC)
  • patible with EL4583 sync separator
  • VCXO, Xtal, or LC tank oscillator
  • < 2ns jitter (VCXO)
  • User controlled PLL capture and lock
  • patible with NTSC and PAL TV formats
  • 8 pre-programmed TV scan rate clock divisors
  • Selectable external divide for custom ratios
  • Single 5V, low current operation

Related Renesas Datasheets

Part Number Description
EL4581 Sync Separator
EL4583 Sync Separator
EL4583A Sync Separator
EL4585 Horizontal Genlock
EL4501 Video Front-End

EL4584 Description

EL4584 Horizontal Genlock, 4FSC The EL4584 is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36MHz. In video applications, this device generates a TTL/CMOS patible Pixel Clock (CLK OUT) which is a multiple of the TV horizontal scan rate and phase locked to it. The reference signal is a horizontal sync signal, TTL/CMOS format, which can be easily...