Octal D-type Flip-Flops (with 3-state outputs)
Mar 30, 2006
These devices are positive edge triggered flip-flops. The difference between HD74HC564 and HD74HC574 is only
that the former has inverting outputs and the latter has noninvertering outputs.
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive
going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all
outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the
• High Speed Operation: tpd (Clock to Output) = 13 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
SOP-20 pin (JEITA)
HD74HC564RPEL SOP-20 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Q0 : level of Q before the indicated Steady-sate input conditions were established.
Q0 : complement of Q0 or level of Q before the indicated Steady-state input Conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 9