HD74HC78 Datasheet | Renesas

Dual J-K Flip-Flops (with Preset, mon Clear and mon Clock) REJ03D0553-0200 (Previous ADE-205-425) Rev.2.00 Oct 06, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a mon clear and a mon clock. Preset and clear are independent of the clock and acplished by a low logic level on the corresponding input. Features - High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF) - High Output Current: Fanout of 10 LSTTL Loads - Wide Operating Voltage: VCC = 2 to 6 V - Low Input...