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HD74LS174P Datasheet

Hex / Quadruple D-type Flip-Flops

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HD74LS174 / HD74LS175
Hex / Quadruple D-type Flip-Flops (with clear)
REJ03D0451–0300
Rev.3.00
Jul.15.2005
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct
clear input, and the HD74LS175 features complementary outputs from each flip-flops. Information at the D inputs
meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.
When the clock input is at either the high or low level, the D input signal has no effect at the outputs.
Features
Ordering Information
HD74LS174
Part Name
Package Type
HD74LS174P
DILP-16 pin
HD74LS174FPEL SOP-16 pin (JEITA)
HD74LS174RPEL SOP-16 pin (JEDEC)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
PRSP0016DG-A
(FP-16DNV)
Package
Abbreviation
P
FP
RP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
HD74LS175
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS175P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74LS175FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
FP
(FP-16DAV)
HD74LS175RPEL SOP-16 pin (JEDEC)
PRSP0016DG-A
(FP-16DNV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Rev.3.00, Jul.15.2005, page 1 of 8


Renesas Electronics Components Datasheet

HD74LS174P Datasheet

Hex / Quadruple D-type Flip-Flops

No Preview Available !

HD74LS174 / HD74LS175
Pin Arrangement
HD74LS174
HD74LS175
Clear 1
1Q 2
1D 3
2D 4
2Q 5
3D 6
3Q 7
GND 8
Q CLR
D CK
D CK
Q CLR
D CK
Q CLR
CLR Q
CK D
CK D
CLR Q
CK D
CLR Q
16 VCC
15 6Q
14 6D
13 5D
12 5Q
11 4D
10 4Q
9 Clock
Clear 1
1Q 2
1Q 3
1D 4
2D 5
2Q 6
2Q 7
GND 8
Q
CLR
CK
Q
D
Q
D
CK
Q CLR
CLR Q
CK
D
Q
D
Q
CK
CLR Q
16 VCC
15 4Q
14 4Q
13 4D
12 3D
11 3Q
10 3Q
9 Clock
(Top view)
(Top view)
Function Table
Inputs
Outputs
Clear
Clock
D
Q
Q
L
X
X
L
H
H
H
H
L
H
L
L
H
H
L
X
Q0
Q0
Notes: 1. H; high level, L; low level, X; irrelevant
2. ; transition from low to high level
3. Q0; the level of Q before the indicated steady-state input conditions were established.
4. Q is applied to HD74LS175 only.
Rev.3.00, Jul.15.2005, page 2 of 8


Part Number HD74LS174P
Description Hex / Quadruple D-type Flip-Flops
Maker Renesas
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HD74LS174P Datasheet PDF






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