Quadruple 2-line-to-1-line Data Selectors / Multiplexers
(with not inverted 3-state outputs)
This multiplexer features three-state outputs that can interface directly with and drive data lines of bus-organized
systems. With all but one of the common outputs disabled (at a high-impedance state) the low impedance of the single
enabled output will drive the bus line to a high or low logic level.
To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output-
enable circuitry is designed such that the output disable times are shorter than the output enable times.
• Ordering Information
HD74LS257FPEL SOP-16 pin (JEITA)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
Rev.3.00, Jul.15.2005, page 1 of 5