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HD74LS259 Datasheet

8-bit Address Latch

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HD74LS259
8-bit Address Latch
REJ03D0471–0200
Rev.2.00
Feb.18.2005
This 8-bit addressable latch is designed for general purpose storage applications in digital systems. Specific uses
include working registers, serial-holding registers, and active-high decoders or demultiplexers. This is multifunctional
device capable of storing single-line data in eight addressable latches, and being a 1-to-8 decoder or demultiplexer with
active-high outputs.
Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function
table. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch.
The addressed latch will follow the data input with all unaddressed latches remaining in their previous states. In the
memory mode, latch remains in their previous states and is unaffected by the data or address inputs.
To eliminate the possibility of entering erroneous data in the latch, the enable should be held high (inactive) while the
address lines are changing.
In the clear mode, all outputs are low and unaffected by the address and data inputs.
Features
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS259P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
HD74LS259FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
HD74LS259RPEL SOP-16 pin (JEDEC)
PRSP0016DG-A
(FP-16DNV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
Rev.2.00, Feb.18.2005, page 1 of 7


Renesas Electronics Components Datasheet

HD74LS259 Datasheet

8-bit Address Latch

No Preview Available !

HD74LS259
Pin Arrangement
Latch
Select
A1
B2
C3
Q0 4
Q1 5
Outputs
Q2 6
Q3 7
GND 8
A
B CLR
CG
Q0 D
Q1 Q7
Q2 Q6
Q3 Q5
Q4
16 VCC
15 Clear
14 Enable
13 Data Input
12 Q7
11 Q6
Outputs
10 Q5
9 Q4
(Top view)
Function Table
CLR
H
H
L
L
Input
G
L
H
L
H
Output of
addressed latch
D
Qio
D
L
Each other output
Qio
Qio
L
L
Function
Addressable latch
Memory
8-line demultiplexer
Clear
Select inputs
Latch addressed
CBA
LLL0
L LH1
LHL 2
L HH 3
HL L 4
HLH5
HHL 6
HHH 7
Notes: 1. H; high level, L; low level
2. D; the level at the data input
3. Oio; the level of Qi (i = 0, 1, 7, as appropriate) before the indicated steady state input conditions were
established.
Rev.2.00, Feb.18.2005, page 2 of 7


Part Number HD74LS259
Description 8-bit Address Latch
Maker Renesas
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HD74LS259 Datasheet PDF






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