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HD74LS273 Datasheet

Octal D-type Positive-edge-triggered Flip-Flops

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HD74LS273
Octal D-type Positive-edge-triggered Flip-Flops (with Clear)
REJ03D0473–0300
Rev.3.00
Jul.15.2005
The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a
direct clear input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse.
When the clock input is at either the high or low level, the D input signal has no effect at the output.
Features
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS273P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
HD74LS273FPEL SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
HD74LS273RPEL SOP-20 pin (JEDEC)
PRSP0020DC-A
(FP-20DBV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Pin Arrangement
Clear 1
1Q 2
1D 3
2D 4
2Q 5
3Q 6
3D 7
4D 8
4Q 9
GND 10
Q
Clear
D CK
D CK
Clear
Q
Q
Clear
D CK
D CK
Clear
Q
Q
Clear
CK D
CK D
Clear
Q
Q
Clear
CK D
CK D
Clear
Q
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 Clock
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 6


Renesas Electronics Components Datasheet

HD74LS273 Datasheet

Octal D-type Positive-edge-triggered Flip-Flops

No Preview Available !

HD74LS273
Function Table
Inputs
Clear
Clock
D
LXX
HH
HL
HLX
Notes: H; high level, L; low level, X; irrelevant
; transition from low to high level
Q0; level of Q before the indicated steady-state input conditions were established.
Block Diagram
1D 2D 3D 4D 5D 6D 7D
Output
Q
L
H
L
Q0
8D
Clock (1)
Clear (2)
DQ
CK
Clear
DQ
CK
Clear
DQ
CK
Clear
DQ
CK
Clear
DQ
CK
Clear
DQ
CK
Clear
DQ
CK
Clear
DQ
CK
Clear
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
Absolute Maximum Ratings
Item
Symbol
Ratings
Supply voltage
VCC
7
Input voltage
VIN 7
Power dissipation
PT 400
Storage temperature
Tstg –65 to +150
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Clock frequency
Clock pulse width
Clear pulse width
Data setup time
Clear (inactive-state) setup time
Data hold time
Symbol
VCC
IOH
IOL
Topr
ƒclock
tw (clock)
tw (clear)
tsu (data)
tsu (clear)
th (data)
Min
4.75
–20
0
20
20
20
25
5
Typ
5.00
25
Max
5.25
–400
8
75
30
Unit
V
V
mW
°C
Unit
V
µA
mA
°C
MHz
ns
ns
ns
ns
ns
Rev.3.00, Jul.15.2005, page 2 of 6


Part Number HD74LS273
Description Octal D-type Positive-edge-triggered Flip-Flops
Maker Renesas
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HD74LS273 Datasheet PDF






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