Renesas Electronics Components Datasheet

HD74LS74AP Datasheet

Dual D-type Positive Edge-triggered Flip-Flops

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Preliminary Datasheet

HD74LS74A

Dual D-type Positive Edge-triggered Flip-Flops

(with Preset and Clear)

R04DS0012EJ0400

(Previous: REJ03D0415-0300)

Rev.4.00

Dec 21, 2011

Features

 Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

HD74LS74AP

DILP-14 pin

PRDP0014AB-B

(DP-14AV)

PRSP0014DF-B

HD74LS74AFPEL SOP-14 pin (JEITA)

(FP-14DAV)

HD74LS74ARPEL SOP-14 pin (JEDEC) PRSP0014DE-A

(FP-14DNV)

Note: Please consult the sales office for the above package availability.

Taping Abbreviation

(Quantity)

—

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

Pin Arrangement

1CLR 1

1D 2

1CK 3

1PR 4

1Q 5

1Q 6

GND 7

CK D

PR CLR

D CK

CLR PR

(Top view)

14 VCC

13 2CLR

12 2D

11 2CK

10 2PR

9 2Q

8 2Q

Function Table

Input

Preset

Clear

Clock

Output



H; high level, L; low level, X; irrelevant, ; transition from low to high level,

Q0; level of Q before the indicated steady-state input conditions were established.

Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.

*;This configuration is nonstable, that is, it will not persist when preset and clear inputs return to their inactive (high) level.

R04DS0012EJ0400 Rev.4.00

Dec 21, 2011

Page 1 of 7

Renesas Electronics Components Datasheet

HD74LS74AP Datasheet

Dual D-type Positive Edge-triggered Flip-Flops

No Preview Available !

HD74LS74A

Preliminary

Absolute Maximum Ratings

Item

Symbol

Ratings

Unit

Supply voltage

Input voltage

Power dissipation

Storage temperature

VCC

VIN

Tstg

400

–65 to +150

C

Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.

Recommended Operating Conditions

Item

Symbol

Supply voltage

VCC

Output current

IOH

IOL

Operating temperature

Topr

Clock frequency

fclock

Pulse width

Clock High

Clear Preset

Setup time

“H” Data

tsu

“L” Data

tsu

Hold time

Note: ; The arrow indicates the rising edge.

Min

4.75

—

–20

20

5

Typ

5.00

—

Max

5.25

–400

—

Unit

A

C

MHz

Electrical Characteristics

(Ta = –20 to +75 °C)

Item

Symbol

min.

typ.* max.

Unit

Condition

Input voltage

Output voltage

VIH

2.0

—

VIL

—

0.8

VOH

2.7

—

VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,

IOH = –400 A

VOL

—

0.5

IOL = 8 mA VCC = 4.75 V, VIL = 0.8 V,

—

0.4

IOL = 4 mA VIH = 2 V

—

Clear

—

Preset

IIH

—

A VCC = 5.25 V, VI = 2.7 V

Clock

—

–0.4

Input

current

Clear

Preset

—

–0.8

IIL

—

–0.8

mA VCC = 5.25 V, VI = 0.4 V

Clock

—

–0.4

—

0.1

Clear

—

0.2

Preset

—

0.2

mA VCC = 5.25 V, VI = 7 V

Clock

—

0.1

Short-circuit output

current

IOS

–20

—

–100

mA VCC = 5.25 V

Supply current

ICC**

—

mA VCC = 5.25 V

Input clamp voltage

VIR

—

–1.5

VCC = 4.75 V, IIN = –18 mA

Notes: * VCC = 5 V, Ta = 25°C

** With all output open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the

clock input is grounded.

R04DS0012EJ0400 Rev.4.00

Dec 21, 2011

Page 2 of 7

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HD74LS74AP Datasheet

Dual D-type Positive Edge-triggered Flip-Flops

HD74LS74AP Datasheet

Dual D-type Positive Edge-triggered Flip-Flops

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