ICS841664I Datasheet | Renesas

Femto Clock® Crystal-to-HCSL Clock Generator DATA SHEET General Description The ICS841664I is an optimized s RIO clock generator and a member of the family of high-performance clock solutions from IDT. The device uses a 25MHz parallel crystal to generate 125MHz and 156.25MHz clock signals, replacing solution requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (<1ps RMS) suitable to clock ponents requiring precise and low-jitter s RIO clock signals. Designed for tele, networking and industrial application, the ICS841664I can also drive the high-speed s RIO Ser Des clock inputs of munication processors, DSPs, switches and bridges. Features - Four differential HCSL clock outputs: configurable for s RIO (125MHz or 156.25MHz) clock signals One REF_OUT LVCMOS/LVTTL clock output - Selectable crystal oscillator interface, 25MHz, 18p F parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input or LVCMOS/LVTTL single-ended input - Supports the following output frequencies: 125MHz or 156.25MHz - VCO: 625MHz - Supports PLL bypass and output enable functions - RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz): 0.45ps (typical) @ 125MHz - Full 3.3V power supply mode - -40°C to 85°C ambient operating temperature - Lead-free (Ro HS 6) packaging Block Diagram XTAL_IN 25MHz XTAL_OUT REF_IN REF_SEL Pulldown Pulldown IREF 0 fref 1 Femto Clock VCO = 625MHz M = ÷25 BYPASS FSEL[0:1]...