Datasheet4U Logo Datasheet4U.com

ICS854S054I - 4:1 Differential-to-LVDS Clock Multiplexer

General Description

The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz.

The ICS854S054I has 4 selectable differential clock inputs.

The PCLK, nPCLK input pairs can accept LVPECL, LVDS or CML levels.

Key Features

  • High speed 4:1 differential multiplexer.
  • One differential LVDS output pair.
  • Four selectable differential PCLK, nPCLK input pairs.
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML.
  • Maximum output frequency: 2.5GHz.
  • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input.
  • Additive phase jitter, RMS: 0.147ps (typical).
  • Part-to-part skew: 300ps (maximum.

📥 Download Datasheet

Datasheet Details

Part number ICS854S054I
Manufacturer Renesas
File Size 1.50 MB
Description 4:1 Differential-to-LVDS Clock Multiplexer
Datasheet download datasheet ICS854S054I Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS854S054I 4:1 Differential-to-LVDS Clock Multiplexer Integrated Device Technology

Other Datasheets by Renesas

Part Number Description
ICS854S058I 8:1 Differential-to-LVDS Clock Multiplexer
ICS854S01I 2:1 Differential-to-LVDS Multiplexer
ICS854S202I-01 Differential-To-LVDS Multiplexer
ICS854S296I-33 LVDS Programmable Delay-Line
ICS854S54I-01 Differential-to-LVDS Multiplexer
ICS854104 Differential-to-LVDS Fanout Buffer
ICS8543 Differential-to-LVDS Fanout Buffer
ICS8543I Differential-to-LVDS Fanout Buffer
ICS8545-02 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
ICS8546-01 Crystal-to-LVDS Fanout Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
4:1 Differential-to-LVDS Clock Multiplexer ICS854S054I DATA SHEET General Description The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.5GHz. The ICS854S054I has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).