ICS9173B Datasheet - Renesas

VIDEO GENLOCK PLL

ICS9173B Features

* Phase-detector/VCO circuit block

* Ideal for genlock system

* Reference clock range 12 kHz to 1 MHz for full output clock range

* Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for c

ICS9173B General Description

The ICS9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when using a low frequen.

ICS9173B Datasheet (327.75 KB)