ICS9173B - VIDEO GENLOCK PLL

Renesas

Datasheet Details

The ICS9173B provide the analog PLL circuit blocks to implement a frequency multiplier.

Phase-detector/VCO circuit block.
Ideal for genlock system.
Reference clock range 12 kHz to 1 MHz for full output clock range.
Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions.
On-chip loop filter.
Single 5 V power supply.
Low power CMOS technology.
8-pin SOIC package Block Diagram IDT® VIDEO.

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Published: Aug 8, 2020 |